ISL6548ACRZA-T Intersil, ISL6548ACRZA-T Datasheet - Page 6

• Manufacturer Part Number: ISL6548ACRZA-T
• Description: IC REG/CTLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6548ACRZA-T

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Other names: ISL6548ACRZA-T

Electrical Specifications
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6548A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6548A enters a reduced
power mode and draws less than 1mA (I
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
Maximum V
LINEAR REGULATORS
DC Gain
Gain Bandwidth Product
Slew Rate
DRIVEn High Output Voltage
DRIVEn Low Output Voltage
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
V
V
PROTECTION
OCSET Current Source
V
V
V
V
V
V
V
Thermal Shutdown Limit
TT_GMCH/CPU
TT_GMCH/CPU
TT_DDR
DDQ
DDQ
TT_DDR
TT_DDR
GMCH
TT_GMCH/CPU
OV Level
UV Level
UV Level
Current Limit
OV Level
UV Level
TT
PARAMETER
Load Current
Rising Threshold
Falling Threshold
UV Level
6
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
CC_S5
V
V
TT
TT
V
V
V
V
I
SYMBOL
VTT_MAX
FB4
FB2
I
FB
FB
GBWP
/V
/V
OCSET
I
I
GATE
GATE
T
R
SR
R
VREF_IN
VREF_IN
) from the
/V
/V
SD
/V
/V
U
L
REF
REF
REF
REF
Periodic load applied with 30% duty cycle and
10ms period using ISL6548A_6506EVAL1
evaluation board (see Application Note AN1124)
Guaranteed By Design
DRIVEn Unloaded
V
V
S0
S0
By Design
S0/S3
S0/S3
S0
S0
S0
S0
By Design
FB
FB
ISL6548A
= 770mV, V
= 830mV, V
TEST CONDITIONS
P12V (Pin 3)
The V
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6548A provide the return path
for the V
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
DRIVEn
DRIVEn
TT
= 0V
= 10V
TT
regulation circuit and the Linear Drivers are
LDO, and switching MOSFET gate drivers. High
9.75
.725
MIN
-3.3
15
18
-3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.700 0.715
TYP
10.0
0.16
1.20
.740
-0.8
115
115
140
0.8
2.5
2.5
1.7
80
20
85
85
85
85
6
-
-
-
MAX
0.50
3.3
22
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
January 3, 2006
UNITS
FN9189.2
MHz
V/µs
mA
mA
kΩ
kΩ
dB
µA
°C
%
%
%
%
%
%
A
A
A
V
V
V
V
A