ISL6537CRZ Intersil, ISL6537CRZ Datasheet - Page 6

• Manufacturer Part Number: ISL6537CRZ
• Description: IC REG/CTLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6537CRZ

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537 enters a reduced
power mode and draws less than 1mA (I
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1μF capacitor.
P12V (Pin 3)
The V
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537 provide the return path
for the V
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
LGATE (Pin 28)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
FB (Pin 15) and COMP (Pin 16)
The V
control loop. FB is the negative input to the voltage loop error
amplifier. The V
resistor divider connected to FB. With a properly selected
divider, V
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for under and overvoltage
events.
TT
DDQ
TT
regulation circuit and the Linear Drivers are
DDQ
switching regulator employs a single voltage
LDO, and switching MOSFET gate drivers. High
can be set to any voltage between the power
DDQ
output voltage is set by an external
6
CC_S5
) from the
ISL6537
PHASE (Pin 24)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
OCSET (Pin 22)
Connect a resistor (R
upper MOSFET. R
(I
set the converter overcurrent (OC) trip point according to the
following equation:
An overcurrent trip cycles the soft-start function.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated V
pins serve as inputs to the V
Reference precision divider.
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connect externally together.
During S0/S1 states, the DDR_VTT pins serve as the
outputs of the V
regulator is disabled.
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the V
regulator. Connect this pin to the V
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of V
reference voltage for the V
recommended that a minimum capacitance of 0.1μF is
connected between V
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, C
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (R
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
The minimum value for C
following equation:
The calculated capacitance, C
capacitor bank on the V
reaching the current limit of the V
I
C
PEAK
OCSET
SS
>
C
------------------------------------------------
=
10 2A R
VTTOUT
), and the upper MOSFET on-resistance (r
I
-------------------------------------------------
OCSET
⋅
r
SS
⋅
DS ON
DDQ
TT
⋅
, connected between VREF_IN and ground
U
xR
(
V
OCSET
||
DDQ
linear regulator. During S3 state, the V
OCSET
R
output. During S0/S1 states, the VDDQ
)
OCSET
L
DDQ
TT
, an internal 20μA current source
SS
rail in a controlled manner without
TT
and VREF_OUT and also
) from this pin to the drain of the
TT
can be found through the
linear regulator. It is
SS
regulator and to the V
, will charge the output
TT
TT
LDO.
TT
output at the physical
and also acts as the
U
||R
L
), sets the
DS(ON)
July 18, 2007
TT
TT
(EQ. 1)
(EQ. 2)
FN9142.6
linear
TT
)