ISL6532AIRZ Intersil, ISL6532AIRZ Datasheet - Page 10

IC REG/CTRLR ACPI DUAL DDR 28QFN

ISL6532AIRZ

Manufacturer Part Number
ISL6532AIRZ
Description
IC REG/CTRLR ACPI DUAL DDR 28QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6532AIRZ

Applications
Memory, DDR/DDR2 Regulator
Current - Supply
5.25mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
and the V
pulled low to disable the backfeed blocking MOSFET.
PGOOD will also transition LOW. When V
internal reference for the V
to the V
floating, the voltage on the V
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V
The V
standby V
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4µs and 8µs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
SLEEP TO ACTIVE (S3 TO S0 TRANSITION)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6532A will enable the V
the V
the NCH pin to a high impedance state turning on the
blocking MOSFET. The AGP LDO goes through a 2048
clock cycle soft-start. The internal short between the V
reference and the V
short, the capacitor on VREF_IN is then charged up through
the internal resistor divider network. The V
follow this capacitor charge up, and acting as the S3 to S0
transition soft-start for the V
is enabled only after 2048 clock cycles, or typically 8.2ms,
have passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
S3
S5
DDQ
DDQ
TT
DDQ
DDQ
standby regulator, enable the V
12V POR
rail. This allows the V
rail will be supported in the S3 state through the
FIGURE 1. TYPICAL COLD START
switching regulator will be disabled. NCH is
LDO. When S3 transitions LOW, the Standby
2048 CLOCK
CYCLES
TT
5VSBY
1V/DIV
500mV/DIV
SOFT-START
rail is released. Upon release of the
INITIATES
V
AGP
TT
12VATX 2V/DIV
DDQ
TT
TT
TT
10
regulator is internally shorted
2048 CLOCK
rail. The PGOOD comparator
rail may not bleed down to 0V.
CYCLES
rail will depend on the
switching regulator, disable
TT
PGOOD COMPARATOR
rail to float. When
SOFT-START ENDS
ENABLED
TT
TT
TT
is disabled, the
LDO and force
output will
500mV/DIV
500mV/DIV
PGOOD
5V/DIV
V
DDQ
V
TT
TT
ISL6532A
should be noted that the soft-start profile of the V
output will vary according to the value of the capacitor on the
VREF_IN pin.
ACTIVE TO SHUTDOWN (S0 TO S5 TRANSITION)
When the system transitions from active (S0) state to
shutdown (S4/S5) state, the ISL6532A IC disables all
regulators and forces the PGOOD pin and the NCH pin
LOW.
V
The overcurrent function protects the switching converter
from a shorted output by using the upper MOSFET ON-
resistance, r
enhances the converter’s efficiency and reduces cost by
eliminating a current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
programs the overcurrent trip level (see Typical Application
Diagrams on page 4 and page 5). An internal 20μA (typical)
current sink develops a voltage across R
referenced to the converter input voltage. When the voltage
across the upper MOSFET (also referenced to the converter
input voltage) exceeds the voltage across R
current function initiates a soft-start sequence. The initiation
of soft-start will affect all regulators. The V
directly affected as it receives it’s reference from V
AGP LDO will also be soft-started, and as such, the AGP
LDO voltage will be disabled while the V
disabled.
Figure 3 illustrates the protection feature responding to an
overcurrent event. At time T0, an overcurrent condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function begins
producing soft-start ramps. The delay interval seen by the
output is equivalent to three soft-start cycles. The fourth
S3
S5
DDQ
V
TT_FLOAT
FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION
Overcurrent Protection (S0 State)
DS(ON)
12V POR
, to monitor the current. This method
2048 CLOCK
CYCLES
12VATX 2V/DIV
PGOOD COMPARATOR
500mV/DIV
V
AGP
ENABLED
DDQ
OCSET
TT
OCSET
regulator is
regulator is
500mV/DIV
500mV/DIV
that is
PGOOD
TT
5V/DIV
V
DDQ
V
, the over-
DDQ
TT
May 5, 2008
LDO
OCSET
FN9099.5
. The
)

Related parts for ISL6532AIRZ