ISL6537ACRZ Intersil, ISL6537ACRZ Datasheet - Page 10

• Manufacturer Part Number: ISL6537ACRZ
• Description: IC REG/CTRLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6537ACRZ

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

allows the termination voltage to float during the S3 sleep
state. When the ISL6537A enables the V
or enters S0 state from a sleep state, this short is released
and the internal divide down resistors which set the
V
controlled voltage rise on the capacitor that is tied to the
VREF_IN pin. The voltage on this capacitor is the reference
for the V
settles to 50% of the V
internal resistors and the V
the rise time of the V
Pin Description section for proper sizing of the VREF_IN
capacitor).
At time t
the V
VIDPGD comparator is enabled. Once enabled if the
V
will be forced to a high impedance state.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6537A will disable all the regulators except for the V
regulator, which is continually supplied by the 5VDUAL rail.
VIDPGD will also transition LOW. When V
internal reference for the V
to the V
floating, the voltage on the V
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V
0V. Figure 1 shows how the individual regulators are
affected by the S3 state at time t
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6537A will initiate the soft-start sequence. This sequence
is very similar to the mechanical start soft-start sequencing.
The transition from S3 to S0 is represented in Figure 1
between times t
At time t
the ATX, which brings up the 12V rail. At time t
has exceeded the POR threshold and the ISL6537A enters a
reset mode that lasts for 3 soft-start cycles. At time t
soft-start cycle reset is ended and the individual regulators
are enabled and soft-started in the same sequence as the
mechanical cold start sequence, with the exception that the
V
Active to Shutdown (S0 to S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6537A IC disables all
regulators and forces the VIDPGD pin LOW. This transition
is represented on Figure 1 at time t
TT_DDR
TT_GMCH/CPU
DDQ
TT_DDR
regulator is already enabled and in regulation.
TT
6
8
TT_DDR
, a full soft-start cycle has passed from the time that
, the SLP_S3 signal transitions HIGH. This enables
voltage to 50% of V
rail. This allows the V
regulator was enabled. At this time the
8
output is within regulation, the VIDPGD pin
regulator and the output will track it as it
and t
TT_DDR
DDQ
14
.
TT
REF_IN
voltage. The combination of the
TT
10
regulator (see the Functional
TT
DDQ_DDR
regulator is internally shorted
rail will depend on the
TT
7
rail may not bleed down to
.
capacitor will determine
15
rail to float. When
.
will provide a
TT_DDR
TT
is disabled, the
9
, the 12V rail
regulator
10
, the 3
DDQ
ISL6537A
Fault Protection
The ISL6537A monitors the V
overvoltage events. The V
protection. The internal V
for under and overvoltage events. All other regulators, with the
exception of the DAC LDO, are monitored for undervoltage
events.
An overvoltage event on either the V
regulator will cause an immediate shutdown of all regulators.
This can only be cleared by toggling the SLP_S5 signal such
that the system enters the S5 sleep state and then
transitions back to the active, S0, state.
If a regulator experiences any other fault condition (an
undervoltage or an overcurrent on V
regulator, and only that regulator, will be disabled and an
internal fault counter will be incremented by 1. If the disabled
regulator is used as the input for another regulator, then that
cascoded regulator will also experience a fault condition due
to a loss of input. The cascoded regulator will be disabled
and the fault counter incremented by 1.
At every fault occurrence, the internal fault counter is
incremented by 1 and an internal Fault Reset Counter is
cleared to zero. The Fault Reset Counter will increment once
for every clock cycle (1 clock cycle is typically 1/250kHz, or
4μs). If the Fault Reset Counter reaches a count of 16384
before another fault occurs, then the Fault Counter is
cleared to 0. If a fault occurs prior to the Fault Reset Counter
reaching a count of 16384, then the Fault Reset Counter is
set back to zero.
The ISL6537A will immediately shut down when the Fault
Counter reaches a count of 4 when the system is restarting
from an S5 state into the active, or S0, state. The ISL6537A
will immediately shut down when the Fault Counter reaches
a count of 5 at any other time.
The 16384 counts that are required to reset the Fault Reset
Counter represent 8 soft-start cycles, as one soft-start cycle is
2048 clock cycles. This allows the ISL6537A to attempt at least
one full soft-start sequence to restart the faulted regulators.
When attempting to restart a faulted regulator, the ISL6537A
will follow the preset start up sequencing. If a regulator is
already in regulation, then it will not be affected by the start
up sequencing.
V
The overcurrent function protects the switching converter from
a shorted output by using the upper MOSFET on-resistance,
r
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
programs the overcurrent trip level (see Typical Application
DS(ON)
DDQ
Overcurrent Protection
, to monitor the current. This method enhances the
TT_DDR
DDQ
DDQ
regulator also has overcurrent
LDO regulator is monitored
regulator for under and
DDQ
DDQ
), then that
or V
TT_DDR
OCSET
FN9143.5
)