ISL6537ACRZ Intersil, ISL6537ACRZ Datasheet - Page 7

• Manufacturer Part Number: ISL6537ACRZ
• Description: IC REG/CTRLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6537ACRZ

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
LGATE (Pin 28)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
FB (Pin 15) and COMP (Pin 16)
The V
control loop. FB is the negative input to the voltage loop error
amplifier. The V
resistor divider connected to FB. With a properly selected
divider, V
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for under and overvoltage
events.
PHASE (Pin 24)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
OCSET (Pin 22)
Connect a resistor (R
upper MOSFET. R
(I
set the converter overcurrent (OC) trip point according to the
following equation:
An overcurrent trip cycles the soft-start function.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated V
I
PEAK
OCSET
DDQ
=
), and the upper MOSFET on-resistance (r
DDQ
I
-------------------------------------------------
OCSET
switching regulator employs a single voltage
r
can be set to any voltage between the power
DS ON
DDQ
DDQ
xR
(
OCSET
OCSET
output. During S0/S1 states, the VDDQ
output voltage is set by an external
)
OCSET
, an internal 20μA current source
) from this pin to the drain of the
7
DS(ON)
(EQ. 1)
)
ISL6537A
pins serve as inputs to the V
Reference precision divider.
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connected externally
together. During S0/S1 states, the DDR_VTT pins serve as
the outputs of the V
V
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the V
regulator. Connect this pin to the V
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of V
reference voltage for the V
recommended that a minimum capacitance of 0.1μF is
connected between V
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, C
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (R
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
The minimum value for C
following equation:
The calculated capacitance, C
capacitor bank on the V
reaching the current limit of the V
BOOT (Pin 25)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
PWM4 (Pin 19)
This pin provides the PWM output for the GMCH core
switching regulator. Connect this pin to the PWM input of an
Intersil MOSFET driver.
FB4 (Pin 19) and COMP4 (Pin 17)
The GMCH core switching regulator employs a single
voltage control loop. FB4 is the negative input to the voltage
loop error amplifier. The GMCH core output voltage is set by
an external resistor divider connected to FB4. With a
properly selected divider, V
between the power rail (reduced by converter losses) and
the 0.8V reference. Loop compensation is achieved by
connecting an AC network across COMP4 and FB4.
The FB4 pin is also monitored for undervoltage events.
C
TT
SS
regulator is disabled.
>
C
------------------------------------------------
10 2A R
VTTOUT
⋅
SS
⋅
⋅
, connected between VREF_IN and ground
U
V
||
DDQ
TT
R
L
DDQ
linear regulator. During S3 state, the
TT
SS
rail in a controlled manner without
TT
and VREF_OUT and also
GMCH
TT
can be found through the
linear regulator. It is
SS
regulator and to the V
, will charge the output
TT
can be set to any voltage
TT
LDO.
TT
output at the physical
and also acts as the
U
||R
L
), sets the
TT
TT
(EQ. 2)
FN9143.5
linear