IC PWR MGMT 5CH W/2 LDO 48QFN

TPS65070RSLR

Manufacturer Part NumberTPS65070RSLR
DescriptionIC PWR MGMT 5CH W/2 LDO 48QFN
ManufacturerTexas Instruments
TPS65070RSLR datasheet
 


Specifications of TPS65070RSLR

ApplicationsMobile/OMAP™Voltage - Supply2.8 V ~ 6.3 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFNLead Free Status / RoHS StatusLead free / RoHS Compliant
Current - Supply-Other names296-24939-2
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Single Chip Power Solution for Battery Powered Systems
Check for Samples: TPS65070, TPS65072, TPS65073,
FEATURES
1
Charger/Power Path Management:
2
– 2A Output Current on the Power Path
– Linear Charger; 1.5A Maximum Charge
Current
– 100mA/500mA/ 800mA/1300mA Current
Limit From USB Input
– Thermal Regulation, Safety Timers
– Temperature Sense Input
3 Step-Down Converters:
– 2.25MHz Fixed Frequency Operation
– Up to 1.5A of Output Current
– Adjustable or Fixed Output Voltage
– V
Range From 2.8V to 6.3V
IN
– Power Save Mode at Light Load Current
– Output Voltage Accuracy in PWM Mode
±1.5%
– Typical 19 μA Quiescent per Converter
– 100% Duty Cycle for Lowest Dropout
LDOs:
– Fixed Output Voltage
– Dynamic Voltage Scaling on LDO2
– 20μA Quiescent Current
– 200mA Maximum Output Current
– V
Range From 1.8V to 6.3V
IN
wLED Boost Converter:
– Internal Dimming Using I2C
– Up to 2 × 10 LEDs
– Up to 25mA per String With Internal Current
Sink
2
I
C Interface
10 Bit A/D Converter
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP, PowerPAD are trademarks of Texas Instruments.
2
UNLESS
OTHERWISE
NOTED
this
document
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Touch Screen Interface
Undervoltage Lockout and Battery Fault
Comparator
APPLICATIONS
Portable Navigation Systems
PDAs, Pocket PCs
OMAP™ and Low Power DSP Supply
DESCRIPTION
The TPS6507x are single chip Power Management
ICs for portable applications consisting of a battery
charger with power path management for a single
Li-Ion or Li-Polymer cell. The charger can either be
supplied by a USB port on pin USB or by a dc voltage
from a wall adapter connected to pin AC. Three
highly efficient 2.25MHz step-down converters are
targeted at providing the core voltage, memory and
I/O voltage in a processor based system. The
step-down converters enter a low power mode at light
load for maximum efficiency across the widest
possible range of load currents. For low noise
applications the devices can be forced into fixed
frequency PWM using the I
step-down converters allow the use of small inductors
and capacitors to achieve a small solution size. The
TPS6507x also integrate two general purpose LDOs
for an output current of 200mA. These LDOs can be
used to power an SD-card interface and an
always-on rail, but can be used for other purposes as
well. Each LDO operates with an input voltage range
between 1.8V and 6.3V allowing them to be supplied
from one of the step-down converters or directly from
the main battery. An inductive boost converter with
two programmable current sinks power two strings of
white LEDs.
The TPS6507x come in a 48-pin leadless package
(6mm × 6mm QFN) with a 0,4mm pitch.
contains
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732
SLVS950B – JULY 2009 – REVISED DECEMBER 2009
TPS650731, TPS650732
2
C interface. The
Copyright © 2009, Texas Instruments Incorporated

TPS65070RSLR Summary of contents

  • Page 1

    ... C Interface • 10 Bit A/D Converter 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OMAP, PowerPAD are trademarks of Texas Instruments. 2 UNLESS OTHERWISE NOTED this document PRODUCTION DATA information current as of publication date ...

  • Page 2

    ... The RSL package is available in tape and reel. Add R suffix (TPS65070RSLR) to order quantities of 2500 parts per reel. Add T suffix (TPS65070RSLT) to order quantities of 250 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) ...

  • Page 3

    ... T Operating ambient temperature A T Operating junction temperature J (1) 6 VSYS whichever is less (2) See application section for more details (3) For proper soft-start Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): (2) (2) (2) (2) (2) TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – ...

  • Page 4

    ... TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com = 25°C (unless A MIN TYP MAX UNIT 2.8 6.3 V 140 19 30 μ μA –2% 2.8 2% 3.0 V 3.1 3.25 360 mV 450 4 ms 150 °C 20 °C 1 SYS 0 0.4 V 0.01 1.0 μA Copyright © 2009, Texas Instruments Incorporated ...

  • Page 5

    ... Oscillator frequency S V Adjustable output voltage range out V Reference voltage ref V Fixed output voltage range out Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TEST CONDITIONS Connected to SYS pin VINDCDC1 = 2.8 V VINDCDC1 = 3.5 V VINDCDC1 = 6.3 V VINDCDC1 = 2.8 V VINDCDC1 = 3 6 for TPS65072, TPS65073, TPS650731, ...

  • Page 6

    ... V 2.1 2.4 3.5 1.95 2.25 2.55 0.6 Vin 600 Copyright © 2009, Texas Instruments Incorporated UNIT μs μs Ω UNIT V mA mΩ μA mΩ μA A MHz V mV ...

  • Page 7

    ... Output voltage specification does not include tolerance of external voltage programming resistors. Output voltage in PFM mode is scaled to +1% of nominal value. (2) Configuration L= 2.2 μ μF OUT Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TEST CONDITIONS Internal resistor divider, I selectable (Default setting) ...

  • Page 8

    ... TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com MIN TYP MAX UNIT (1) 1.8 6.3 V 1.0 3.3 V 0.725 3.3 V 200 mA 1.8 1.2 V 1.8 1.2 1.2 V 1.8 200 mA 400 mA 400 mA 150 mV 150 mV –1% 1.5% –1% 1% –1% 1% –2.5% 2.5% 400 Ω 250 μs Copyright © 2009, Texas Instruments Incorporated ...

  • Page 9

    ... Reset, PB_OUT, PGood,INT output leakage current V Threshold voltage at THRESHOLD pin th V Hysteresis on THRESHOLD pin th_hyst I Input bias current at EN_wLED, THRESHOLD in Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 TEST CONDITIONS Isink1 = Isink2 = 20 mA, Vin = 2 3 25° ...

  • Page 10

    ... MIN TYP MAX UNIT 20 μA 2.75 V 150 μA Copyright © 2009, Texas Instruments Incorporated ...

  • Page 11

    ... If the DPPM threshold is lower than the battery voltage, supplement mode will be engaged first and the SYS voltage will chatter around the battery voltage; during that condition no DPPM mode is available. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 ...

  • Page 12

    ... CHG CHG CHG 0.08× 0.1× 0.13× CHG CHG CHG 25 ms 150 100 65 mV 125 250 –15% 15 min 2×T h CHG –2% 7.35 2% kΩ –2% 62.5 2% kΩ 860 1660 2000 Copyright © 2009, Texas Instruments Incorporated ...

  • Page 13

    ... I Clock input for the I2C interface. SDAT 27 I/O Data line for the I2C interface. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 TEST CONDITIONS If temperature is exceeded, charge current is reduced DEVICE INFORMATION ...

  • Page 14

    ... Enable input for TPS6507x. When pulled LOW, the DCDC converters and LDOs start with the sequencing PB_IN programmed internally. Internal 50k pull-up resistor to AVDD6 14 Submit Documentation Feedback Product Folder Link(s): PIN FUNCTIONS (continued) DESCRIPTION TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Copyright © 2009, Texas Instruments Incorporated ...

  • Page 15

    ... The output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2..0] = 100 or DCDC_SQ[2..0] = 111. PowerPAD™ Power ground connection for the PMU. Connect to GND Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PIN FUNCTIONS (continued) ...

  • Page 16

    ... TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com SYS SYS AVDD6 4 Batt Batt TS INT_LDO BYPASS SCLK SDAT Power_ON PB_OUT PGOOD 2 VI/O VDCDC1 PGND1 2 Vmem VDCDC2 PGND2/PAD 2 Vcore VDCDC3 PGND3/PAD VLDO1 VLDO1 2 VLDO2 VLDO2 2 FB_wLED Isink1 Isink2 PGND4/PAD Reset (EN_EXTLDO ) Copyright © 2009, Texas Instruments Incorporated ...

  • Page 17

    ... Startup DCDC1, DCDC2 and DCDC3, LDO1, LDO2 Load transient response LDO1 Line transient response LDO1 SET ISET wLED efficiency vs duty cycle wLED efficiency vs input voltage Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TYPICAL CHARACTERISTICS V = 3.3V 3.0V, 3.6V, 4.2V 3.3V ...

  • Page 18

    ... LOAD CURRENT/PFM MODE 100 0.0001 0.001 TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com EFFICIENCY DCDC1 vs 3.4V 3. PWM Mode 25°C 0.01 0 Output Current - A O Figure 2. EFFICIENCY DCDC2 PWM Mode 25°C 0.01 0 Output Current - A O Figure 4. Copyright © 2009, Texas Instruments Incorporated ...

  • Page 19

    ... I - Output Current - A O Figure 5. EFFICIENCY DCDC3 vs LOAD CURRENT/PWM MODE 100 PWM Mode 90 25° 3. 0.0001 0.001 0.01 0 Output Current - A O Figure 7. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): 100 90 3. 0.0001 100 PWM Mode 90 25° 3. ...

  • Page 20

    ... LOAD TRANSIENT RESPONSE V DCDC2 (Offset: 1.8 V) OUT I DCDC2 Load TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com EFFICIENCY DCDC3 vs 3V 4.2V 5V 0.01 0 Output Current - A O Figure 10. CONVERTER 2 V DCDC3 = 3 Load mA - 1350 mA - 150 mA Figure 12. Copyright © 2009, Texas Instruments Incorporated ...

  • Page 21

    ... CONVERTER 2 V DCDC2 (Offset: 1.75 V) OUT V DCDC2 (Offset 3 3.6V, IN Load = 1.5 A Figure 15. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 LINE TRANSIENT RESPONSE V DCDC1 (Offset: 3.25 V) OUT V DCDC1 (Offset LINE TRANSIENT RESPONSE V DCDC3 (Offset: 1 ...

  • Page 22

    ... DCDC2 (Offset: 1.8 V) OUT I DCDC2 L LOAD TRANSIENT RESPONSE LDO1 V LDO1 (Offset: 1.8 V) OUT I LDO1 LOAD TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com CONVERTER 2 – PFM MODE Load = 15 mA PFM Figure 18 LDO1 = 3.6 V, bat IN LOAD = 180 mA Figure 20. Copyright © 2009, Texas Instruments Incorporated ...

  • Page 23

    ... EFFICIENCY vs Duty Cycle 100 2x6 LEDs each Duty Cycle - % Figure 23. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): 1200 1150 1100 1050 1000 950 900 0.1 100 2x6 LEDs 20 mA each 2.8 3 100 TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 ...

  • Page 24

    ... Short Detect V DPPM V OUT DAC Sys V BAT(REG VSYS Supplement IBAT(SC) I²C V BAT(SC LOWV V RCH ADC3 I BAT (DET) DAC I²C I²C V THRON D THCHG ADC4 V HOT(45) t DGL(TS) V COLD (0) I²C V DIS(TS) I²C EN Copyright © 2009, Texas Instruments Incorporated www.ti.com SYS ISET BAT BAT_sense TS ...

  • Page 25

    ... IC junction temperature and reduces the charge current if the internal temperature threshold is exceeded. Figure 27 shows what happens in each of the three phases: Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): . During the power down mode the host commands at the control pins are Figure 26 ...

  • Page 26

    ... OUT pin, if any). In this case, the charger (Vset-100mV), a check is performed to see whether the battery RCH is pulled from the battery for a duration t TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com DONE TERM CURRENT = 1 . The battery voltage CHG BAT(REG) (1) ( the voltage on the BAT pin DET Copyright © 2009, Texas Instruments Incorporated . ...

  • Page 27

    ... In each of these events, the internal timers are slowed down proportionately to the reduction in charging current. Note also that whenever any of these events occurs, termination detection is disabled. A modified charge cycle with the thermal loop active is shown in Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): in the battery detection test, it indicates that the battery has been ...

  • Page 28

    ... CV TAPER REGULATION CHARGE Battery Current IC junction temperature, T Figure 28. Thermal Loop in time t during pre-charging LOWV PRECHG in time t in fast charge (measured from beginning of fast TERM MAXCH TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com DONE TERM CURRENT = 1 J Copyright © 2009, Texas Instruments Incorporated ...

  • Page 29

    ... The TPS6507x step down converters operate with typically 2.25MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converter automatically enters Power Save Mode and operates in Pulse Frequency Modulation (PFM) . Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): resistor value in parallel to the NTC ...

  • Page 30

    ... Table Table 1. Default Voltages DCDC2 DEFDCDC2=HIGH 1.8 V 3.3 V 1.8 V 2.5 V 1.2 V 1.8 V 1.2 V 1.8 V 1.8 V 3.3 V TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com 1. DCDC3 DEFDCDC3=LOW DEFDCDC3=HIGH 1.0 V 1.2 V 1.2 V 1.4 V 1.2 V 1.35 V 1.2 V 1.35 V 1.2 V 1.35 V Copyright © 2009, Texas Instruments Incorporated ...

  • Page 31

    ... PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the Low Side MOSFET switch. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 +1%, the device starts a PFM pulse ...

  • Page 32

    ... The Soft start circuit is enabled after the start up time t During soft start, the output voltage ramp up is controlled as shown OUT 32 Submit Documentation Feedback Product Folder Link(s max Start RAMP Figure 31. Soft Start TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com (3) has expired. Start Figure 31. Copyright © 2009, Texas Instruments Incorporated (3) ...

  • Page 33

    ... Bit MASK DCDC2 is set to 1, the PGOOD pin will be driven low as long as the output of DCDC2 is below the target voltage. If the output voltage of DCDC2 rises to its nominal value, the PGOOD pin will be released after the delay time defined. See the default settings in the register description. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THRESHOLD ...

  • Page 34

    ... POWER POWER_ON=1 OFF 3 SYS = ON POWER_ON=0 POWER POWER POWER_ON=1 ON_1 ON_2 SYS = ON SYS = ON Figure 33. State Machine TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 all voltages powered down DCDC converters power down LDOs power down depending on sequencing option Copyright © 2009, Texas Instruments Incorporated www.ti.com ...

  • Page 35

    ... ENABLE ISINK as it enables the current sink for the white LEDs. Once enabled, an output voltage is automatically generated at FB_wLED, high enough to force the programmed current through the string of white LEDs. Two strings of white LEDs can be powered. The current in each of the two strings is regulated by an Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): 33. ...

  • Page 36

    ... Using these relationships, the touch screen interface can make measurements of either position or pressure. 36 Submit Documentation Feedback Product Folder Link(s): /Rset × ISET ISET Figure 35. The points shown in the diagram as TSX1, TSX2, TSY1 and TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Copyright © 2009, Texas Instruments Incorporated ...

  • Page 37

    ... INT. Once the host detects the interrupt signal, will enable the ADC converter and set the TSC_M<2:0> 2 via the I C bus to select any of five measurements (position, pressure, plate) as shown in Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): X-Plate TSX1 ...

  • Page 38

    ... ADRESULT / 1024 pos pos VTSREF – ADC ADRESULT / 1024 pos – R //R – VTSREF/ [(V / 22k) × 150] ADC R // × X × (1 – pos pos R // × Y × (1 – pos pos TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com x2 y2 Copyright © 2009, Texas Instruments Incorporated ...

  • Page 39

    ... TSX1 I L PMOS I L/150 TGATE TSREF TO ADC TGATE 22 kW NMOS TSX2 X PLATE RESISTANCE MEASUREMENT Figure 37. Two Plate Resistance Measurement Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TO ADC TO ADC TSX1 TSY1 TGATE TGATE TSY2 Figure 35. Two Position Measurement TSX1 I L /150 ...

  • Page 40

    ... Product Folder Link(s): TSX1 TGATE TRESHOLD DETECTOR TGATE TSX2 STANDBY MODE Figure 38. Touch Screen Standby Mode 2 Data line Change stable; of data data valid allowed TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 TSY1 NMOS NMOS TSY2 C specifications, allowing transfers Copyright © 2009, Texas Instruments Incorporated www.ti.com ...

  • Page 41

    ... Figure 42. Serial I/f READ from TPS6507x: Protocol A SCLK ... SDAT .. A6 A0 R/W ACK 0 0 Start Slave Address Figure 43. Serial I/f READ from TPS6507x: Protocol B Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): Figure 40. START and STOP Conditions ... ... R/W ACK ACK 0 0 Register Address Figure 41 ...

  • Page 42

    ... Product Folder Link(s (HIGH) t su(STA) t h(DATA) t su(DATA) Figure 44. Serial I/f Timing Diagram TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com t h(STA) t su(STO) STA MIN MAX 400 600 1300 300 300 600 600 0 100 600 1300 Copyright © 2009, Texas Instruments Incorporated STO UNIT kHz ...

  • Page 43

    ... USB input is 500 mA max 10 = input current from USB input is 800 mA max 11 = input current from USB input is 1300 mA max Note: safety timers are cleared if the input voltage at both AC and USB are removed. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s ...

  • Page 44

    ... Cleared when Cleared when Cleared when Cleared when read UVLO UVLO R TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com USB or AC USB or AC PB_IN input voltage input voltage INT applied removed read read read UVLO UVLO UVLO Copyright © 2009, Texas Instruments Incorporated ...

  • Page 45

    ... Bit 0 BAT TEMP ERROR battery temperature is in the allowed range for charging temperature sensor detected Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s DPPM ...

  • Page 46

    ... Safety timer SENSOR timer value0 enable TYPE UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Charge Charger Suspend Charger Termination reset Charge ON/OFF UVLO UVLO UVLO R/W R/W R/W Copyright © 2009, Texas Instruments Incorporated BO enable 1 UVLO R/W ...

  • Page 47

    ... DPPM loop is active Bit 6 PRECHARGE VOLTAGE 0 = pre-charge to fast charge transition voltage is 2. pre-charge to fast charge transition voltage is 2.9V Bit 5..4 CHARGE VOLTAGE SELECTION0/ 4.10V 01 = 4.15V 10 = 4.20V 11 = 4.25V Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s Charge Charge voltage voltage voltage selection1 ...

  • Page 48

    ... Termination Precharge DPPM DPPM time threshold0 UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Termination Charger current current active Isink at USB factor1 factor0 UVLO UVLO UVLO R/W R/W R Copyright © 2009, Texas Instruments Incorporated BO Disable 0 UVLO R/W ...

  • Page 49

    ... INPUT SELECT – see table INPUT INPUT SELECT_3 SELECT_2 SELECT_1 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s End of Vref enable start conversion SELECT_3 UVLO UVLO UVLO R/W R R/W INPUT INPUT FULL SCALE SELECT_0 INPUT VOLTAGE 0 0 2.25V 0 1 2.25V 1 0 2.25V 1 1 2.25V ...

  • Page 50

    ... Voltage TSX1 Pressure Current TSX1 and TSX2 Plate X Current TSX1 Plate Y Current TSY1 TSC standby Voltage TSX1 and TSX2 A/D Voltage measurement with ADC TSC and ADC disabled (no interrupt generation AD_BIT2 AD_BIT1 AD_BIT0 LSB Copyright © 2009, Texas Instruments Incorporated BO 1 UVLO R ...

  • Page 51

    ... LDO1 output voltage is within its nominal range. Bit 0 PGOOD LDO2 indicates that the LDO2 output voltage is below its target regulation voltage or disabled indicates that the LDO2 output voltage is within its nominal range. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s ...

  • Page 52

    ... Product Folder Link(s MASK MASK VDCDC3 and VDCDC1 VDCDC2 LDO1 UVLO UVLO R R/W R/W TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com MASK MASK MASKLDO1 VDCDC3 UVLO UVLO UVLO R/W R/W R/W Copyright © 2009, Texas Instruments Incorporated BO MASK LDO2 0 0 UVLO R/W ...

  • Page 53

    ... ON-state. The enable pins for the converters that are automatically enabled, should be tied to GND. For sequencing option DCDC_SEQ=111, the start is initiated by going into ON-state, however, the external LDO connected to pin EN_EXTLDO is powered first, followed by LDO2. (The sequencing of LDO1 and LDO2 is defined in register LDO_CTRL1) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s ...

  • Page 54

    ... EN_DCDC3 PIN 54 Submit Documentation Feedback Product Folder Link(s): EN_DCDC2 PIN disabled disabled enabled CON_CTRL1<2> DCDC3 CONVERTER TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com CON_CTRL1<3> DCDC2 CONVERTER 0 x disabled 1 0 disabled 1 1 enabled disabled disabled enabled Copyright © 2009, Texas Instruments Incorporated ...

  • Page 55

    ... Note: The undervoltage lockout voltage is sensed at the SYS pin and the device goes to OFF state when the voltage is below the value defined in the register. BG_GOOD is the internal bandgap good signal which occurs at lower voltages than UVLO. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): B6 ...

  • Page 56

    ... UVLO UVLO UVLO R R/W R/W TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 DCDC2 DCDC3 LDO1 discharge discharge discharge UVLO UVLO UVLO R/W R/W R DCDC1[2] DCDC1[1] DCDC1[ UVLO UVLO UVLO R/W R/W R/W Copyright © 2009, Texas Instruments Incorporated www.ti.com BO LDO2 1 UVLO R UVLO R/W ...

  • Page 57

    ... DEFDCDC3_HIGH depending on the status of the DEFDCDC3 pin. IF DEFDCDC3 is LOW the value in DEFDCDC3_LOW is selected, if DEFDCDC3 = HIGH, the value in DEFDCDC3_HIGH is selected. Per default the converter is internally fixed but can be programmed to an externally adjustable version by EEPROM similar to DCDC2. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s ...

  • Page 58

    ... Submit Documentation Feedback Product Folder Link(s TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Copyright © 2009, Texas Instruments Incorporated ...

  • Page 59

    ... DEFDCDC2 or DEFDCDC3 pin voltage change is done internally be re-programming DEFDCDC3_HIGH, the voltage change is initiated immediately after the new value has been written to the register with the slew rate defined. SLEW2 SLEW SLEW Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s ...

  • Page 60

    ... DCDC converters have an internal 170us delay as well. 60 Submit Documentation Feedback Product Folder Link(s LDO_SQ0 LDO1[3] Table 9 See Table 9 0 UVLO UVLO R/W R/W R TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com LDO1[2] LDO1[1] LDO1[ UVLO UVLO UVLO R/W R/W R/W Copyright © 2009, Texas Instruments Incorporated UVLO R/W ...

  • Page 61

    ... DEFLDO2 1 = the output voltage follows the setting defined for DCDC3 (DEFDCDC3_LOW or DEFDCDC3_HIGH, depending on the state of pin DEFDCDC3) Bit 5..0 LDO2[5] to LDO2[0]: output voltage setting for LDO2 similar to DCDC3 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): LDO1[2] LDO1[1] LDO1[0] 0 ...

  • Page 62

    ... CYCLE_6 CYCLE_5 CYCLE_4 UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 LED DUTY LED DUTY LED DUTY CYCLE_3 CYCLE_2 CYCLE_1 UVLO UVLO UVLO R/W R/W R/W Copyright © 2009, Texas Instruments Incorporated www.ti.com LED DUTY CYCLE_0 0 UVLO R/W ...

  • Page 63

    ... Please refer to for recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Just for completeness the RMS ripple current is calculated as: Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): APPLICATION INFORMATION Table 4 ...

  • Page 64

    ... Cout è ø Table 5. Possible Capacitors 0805 TDK C2012X5R0J226MT 0805 Taiyo Yuden JMK212BJ226MG 0805 Taiyo Yuden JMK212BJ106M 0805 TDK C2012X5R0J106M TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com (6) (7) Ceramic Ceramic Ceramic Ceramic Copyright © 2009, Texas Instruments Incorporated ...

  • Page 65

    ... Rds(on) = 0.6R — drain-source resistance of the internal NMOS switch Vsw — voltage drop at the internal NMOS switch I — average current in NMOS when turned on AVG Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 (8) (9) ...

  • Page 66

    ... Table 6. Tested Inductors INDUCTOR TYPE INDUCTOR VALUE LPS3015 18 μH LPS4018 47 μH LPS4018 47 μH TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com 140 mV » = 117 mA Table 6 with the test conditions as SUPPLIER Coilcraft Coilcraft Coilcraft Copyright © 2009, Texas Instruments Incorporated (10) (11) (12) (13) (14) (15) (16) (17) ...

  • Page 67

    ... The charger supports two different resistor values for the NTC. The default is internally programmed to 10k possible to change to a 100k NTC with the I2C interface. RESISTANCE AT 25°C 10k 100k Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): Table 7. Tested Capacitor CAPACITOR CAPACITOR ...

  • Page 68

    ... Submit Documentation Feedback Product Folder Link(s): RT1 TS 2.25 V RT2 V (45) HOT + - + V (0) COLD - Figure 45. Linearizing the NTC 46. RT1 RT3 TS 2.25 V RT2 V (45) HOT + - + V (0) COLD - TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Table 8. NTC NTC Copyright © 2009, Texas Instruments Incorporated (18) ...

  • Page 69

    ... Therefore RT3 is needed to shift the temperature range to higher temperatures again. for: • RT2 = 47k • RT3 = 820R Using these values will extend the temperature range for charging to –5°C to 50°C. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): RNTC ( ...

  • Page 70

    ... VDCDC1, VDCDC2, VDCDC3 001 DCDC1=VDDS1-5 (1.8V) DCDC2=VDDSHV (3.3V) DCDC3=VDD_CORE (1.2V) LDO1=VDDA1P8V (1.8V) LDO2=VDDS_DPLL (1.8V) PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com COMMENT Copyright © 2009, Texas Instruments Incorporated ...

  • Page 71

    ... The VDCDCx line should be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, L3 and L4 traces). See the EVM users guide for details about the layout for TPS6507x. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 ...

  • Page 72

    ... DVDD3318_B (3.3V or 1.8 V) DVDD3318_C (3.3V or 1.8 V) CVDD (1.2 V) SATA_VDD (1.2 V) PLL0_VDDA (1.2 V) PLL1_VDDA (1.2 V) USBs CVDD (1.2 V) VDDARNWA/1 (1.2 V) SATA_VDDR (1.8 V) USB0_VDDA18 (1 USB1_VDDA18 (1.8 V) DDR_DVDD18 (1.8 V) VDDIO PB_INTERRUPT RESET SDAT SCLK INT GPIO (power hold) Copyright © 2009, Texas Instruments Incorporated ...

  • Page 73

    ... V 170 s m VLDO1 (SATA_VDDR) 1.8 V VDCDC1 (USB0_VDDA33) 3.3 V PGOOD ( Reset ) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): can be released HIGH any time after POWR_ON = HIGH asserted HIGH by the application processor any time while m 250 s m 250 s m 170 s m 400 ms Figure 50 ...

  • Page 74

    ... TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com ALTAS IV VCC_3V3 (VDDIO) VCC_1V8 (VDDIO_MEM) VDD_PDN (1.2 V) VDD_PRE (1.2 V) VDDPLL (1.2 V) VDD_RTCIO GPIO (enable wLED) GPIO (power hold) X_PWR_EN VIO PB_INTERRUPT RESET SDAT SCLK INT Note: /Reset to Atlas 4 may need delay from VDDIO Copyright © 2009, Texas Instruments Incorporated ...

  • Page 75

    ... EN_DCDC3 (X_PWR_EN) VDCDC3 (VDD_PDN) VLDO1 (VDDPLL) PGOOD (X_RESET_B) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): can be released HIGH any time after POWR_ON=HIGH asserted HIGH by the application processor any time while /PB_IN=LOW to keep the system alive 0.95 x Vout,nominal 0.95 x Vout,nominal ...

  • Page 76

    ... OFF state instead of exit from DEEP SLEEP and Sirf PRIMA would read DS_RDY=0, which indicates memory data is not valid. See timing diagrams for Sirf Prima SLEEP and DEEP SLEEP in 76 Submit Documentation Feedback Product Folder Link(s): Figure 53 and TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Figure 54. Copyright © 2009, Texas Instruments Incorporated ...

  • Page 77

    ... VLDO1 (VDDPLL) PGOOD (X_RESET_B) Figure 53. Timing for Sirf Prima SLEEP Mode Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): can be released HIGH any time after POWR_ON=HIGH asserted HIGH by the application processor any time while /PB_IN=LOW to keep the 0.95 x Vout,nominal 1ms 0 ...

  • Page 78

    ... Bits PWR_DS to set Titan 2 to DEEP SLEEP mode 20ms TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com wakeup from DEEP SLEEP 0.95 x Vout,nominal DS_RDY is cleared by user software PWR_DS is cleared by PB_IN going LOW 20ms Copyright © 2009, Texas Instruments Incorporated ...

  • Page 79

    ... BYPASS INT_LDO L4 SYS FB_wLED 1uF ISINK1 wLED boost ISINK2 ISET1 ISET2 THRESHOLD - delay + Figure 55. OMAP35xx (Supporting SYS-OFF Mode) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS79901 Vin BAT SYS BAT EN LiIon TS NTC SYS VINDCDC1/2 VINDCDC3 2 x 10uF 1.5uH L1 DCDC1 ...

  • Page 80

    ... Product Folder Link(s): can be released HIGH any time after POWR_ON=HIGH asserted HIGH by the application processor (OMAP) any time while /PB_IN=LOW to keep the system alive 250 s m 250 s m 250 s m 400ms TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com Copyright © 2009, Texas Instruments Incorporated ...

  • Page 81

    ... SYS 1uF PB_IN ON / OFF AD_IN1 (TSX1) AD_IN2 (TSX2) AD_IN3 (TSY1) AD_IN4 (TSY2) L4 SYS FB_wLED ISINK1 wLED boost ISINK2 ISET1 ISET2 THRESHOLD - + Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): BAT BAT LiIon TS NTC SYS VINDCDC1/2 VINDCDC3 2 DCDC1 VDCDC1 600mA 2 DCDC2 ...

  • Page 82

    ... HIGH by the application processor any time while /PB_IN=LOW to keep the 250 s m 250 s m 250 s m 170 enabled by OMAP35xx by I2C command 400ms Figure 58. TPS650731: OMAP35xx timing TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 50ms debounce system alive Copyright © 2009, Texas Instruments Incorporated www.ti.com ...

  • Page 83

    ... AD_IN4 (TSY2) L4 SYS FB_wLED 1uF ISINK1 wLED boost ISINK2 ISET1 ISET2 THRESHOLD - delay + Figure 59. Powering AM3505 Using TPS650732 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): BAT BAT LiIon TS NTC SYS VINDCDC1/2 VINDCDC3 2 x 10uF 2.2uH L1 DCDC1 600mA VDCDC1 10uF 2 ...

  • Page 84

    ... Product Folder Link(s): can be released HIGH any time after POWR_ON=HIGH 50ms debounce asserted HIGH by the application processor any time while /PB_IN=LOW to keep the 250us 250us 170us 400ms TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 www.ti.com system alive Copyright © 2009, Texas Instruments Incorporated ...

  • Page 85

    ... Deleted "Product Preview" footnote in reference to the TPS65072 device status. ............................................................ • Changed Schematic entity part number from OMAP3505 to AM3505 ............................................................................... Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SLVS950B – JULY 2009 – REVISED DECEMBER 2009 TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 ...

  • Page 86

    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status TPS65070RSLR ACTIVE VQFN TPS65070RSLT ACTIVE VQFN TPS65072RSLR ACTIVE VQFN TPS65072RSLT ACTIVE VQFN TPS650731RSLR ACTIVE VQFN TPS650731RSLT ACTIVE VQFN TPS650732RSLR ACTIVE VQFN TPS650732RSLT ACTIVE VQFN TPS65073RSLR ACTIVE VQFN TPS65073RSLT ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs ...

  • Page 87

    Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants ( not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak ...

  • Page 88

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TPS650731RSLR VQFN RSL TPS650731RSLT VQFN RSL TPS650732RSLR VQFN RSL TPS650732RSLT VQFN RSL TPS65073RSLR VQFN RSL TPS65073RSLT VQFN RSL PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 ...

  • Page 89

    Device Package Type TPS650731RSLR VQFN TPS650731RSLT VQFN TPS650732RSLR VQFN TPS650732RSLT VQFN TPS65073RSLR VQFN TPS65073RSLT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RSL 48 2500 RSL 48 250 RSL 48 2500 RSL 48 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...