ISL6532ACR Intersil, ISL6532ACR Datasheet - Page 13

• Manufacturer Part Number: ISL6532ACR
• Description: IC REG/CTRLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6532ACR

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 5.25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -

The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ΔV
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6532A) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180°. The following equations relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F LC
ΔV
1. Pick Gain (R
3. Place 2
4. Place 1
2. Place 1
3
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
, C
OSC
=
FB
1
V
------------------------------------------ -
2π x
, C
DDQ
. The goal of the compensation network is to provide
OSC
2
ST
, and C
ND
ST
0dB
OUT
COMPARATOR
=
L O x C O
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
1
Zero Below Filter’s Double Pole (~75% F
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
Pole at the ESR Zero.
V
Zero at Filter’s Double Pole.
ISL6532A
0.8
) and adequate phase margin. Phase margin
E/A
2
PWM
/V
/R
×
3
Z
+
E/A
-
) in Figure 5. Use these guidelines for
⎛
⎜
⎝
1
FB
-
+
COMP
LC
1
) for desired converter bandwidth.
C
+
. This function is dominated by a DC
REFERENCE
2
REFERENCE
and a zero at F
R
------ -
R
C
1
4
-
+
1
⎞
⎟
⎠
O
DRIVER
DRIVER
R
13
F ESR
and C
Z
2
IN
OSC
FB
=
O
Z
FB
), with a double pole
------------------------------------------- -
2π x ESR x C O
ESR
.
PHASE
R
(PARASITIC)
V
4
C
IN
3
IN
L
Z
R
. The DC Gain of
IN
O
1
1
) divided by the
R
ESR
C
3
O
V
DDQ
0dB
V
(EQ. 4)
LC
1
DDQ
, R
and
).
IN
2
ISL6532A
,
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at f
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45 °.
Include worst case component variations when determining
phase margin.
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This
LDO, which uses a MOSFET as the linear pass element,
requires feedback compensation to insure stability of the
system. The LDO requires compensation because of the
output impedance of the error amplifier.
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
f
f
80
60
40
20
Z1
Z2
0
and Z
=
=
10
(R
20LOG
----------------------------------- -
2π x R
------------------------------------------------------ -
2π x R
MODULATOR
2
IN
/R
ND
1
to provide a stable, high bandwidth (BW) overall
GAIN
)
(
100
1
Pole at Half the Switching Frequency.
2
1
x C
1
+
R
2
3
1k
) x C
f
Z1
f
LC
FREQUENCY (Hz)
f
Z2
3
10k
f
P1
f
f
f
ESR
P1
P2
(V
IN
100k
20LOG
=
=
f
/ΔV
P2
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
OSC
P2
OPEN LOOP
ERROR AMP GAIN
with the
1M
)
1
2
3
COMPENSATION
x
x C
CLOSED LOOP
1
⎛
⎜
⎝
C
--------------------- -
C
10M
3
GAIN
1
1
GAIN
+
x C
May 5, 2008
C
FN9099.5
(EQ. 5)
2
2
⎞
⎟
⎠