IC REG/CTRLR ACPI DUAL DDR 20QFN

ISL6532BCR

Manufacturer Part NumberISL6532BCR
DescriptionIC REG/CTRLR ACPI DUAL DDR 20QFN
ManufacturerIntersil
ISL6532BCR datasheet
 


Specifications of ISL6532BCR

ApplicationsMemory, DDR/DDR2 RegulatorCurrent - Supply5.25mA
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case20-QFNLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Voltage - Supply-  
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Data Sheet
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532B provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply V
with high current during
DDQ
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (V
/2) high current V
DDQ
TT
need for a negative supply. A buffered version of the V
reference is provided as V
.
REF
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
±
static regulation tolerance of
2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings V
in a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD
signal indicates that all supplies are within spec and
operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the V
and V
TT
regulators. Thermal shutdown is integrated.
Pinout
ISL6532B (QFN)
TOP VIEW
20 19 18 17 16
5VSBY
1
GND
2
VTT
3
VTT
4
VDDQ
5
6
7
8
9
10
1
Features
• Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate V
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
• Integrated V
voltage without the
• PWM Controller Drives Low Cost N-Channel MOSFETs
/2
DDQ
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- Both Outputs:
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection on V
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
into regulation
DDQ
PCB Efficiency, Thinner in Profile
• Pb-free available
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
standby
DDQ
• Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
NCH
15
PART NUMBER
14
PGOOD
ISL6532BCR
13
GND
ISL6532BCRZ
COMP
12
(See Note)
FB
11
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
All other trademarks mentioned are the property of their respective owners.
ISL6532B
July 2004
FN9120.3
/2 Divider Reference
DDQ
Buffer
REF
±
2% Over Temperature
and Under/Over-Voltage
TT
TEMP. RANGE
o
(
C)
PACKAGE
PKG. DWG. #
0 to 70
20 Ld 6x6 QFN
L20.6x6
0 to 70
20 Ld 6x6 QFN
L20.6x6
(Pb-free)
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved.

ISL6532BCR Summary of contents

  • Page 1

    ... NCH 15 PART NUMBER 14 PGOOD ISL6532BCR 13 GND ISL6532BCRZ COMP 12 (See Note *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations ...

  • Page 2

    Block Diagram P3V3SBY VDDQ S3 REGULATOR VDDQ(2) VTTSNS VTT REG VTT(2) DISABLE { R U VREF_IN { R L UV/OV VREF_OUT SLP_S3# SLP_S5# 5VSBY VOLTAGE REFERENCE 0.800V 0.680V (-15%) 0.920V (+15%) 5V POR S3 SLEEP, SOFT-START, PGOOD, AND FAULT PWM ...

  • Page 3

    Simplified Power System Diagram SLP_S3 SLP_S5 5VSBY/3V3SBY Typical Application - 5V or 3.3V Input +3.3V PGOOD V DDQ SLP_S3 SLP_S5 V REF VTT 3 ISL6532B 12V 5VSBY SLEEP STATE LOGIC PWM CONTROLLER STANDBY LDO ISL6532B VTT ...

  • Page 4

    Typical Application - Input From 5V Dual +3.3V PGOOD V DDQ SLP_S3 SLP_S5 V REF VTT 4 ISL6532B 5VSBY +12V C BP S3# NCH S5# VREF_OUT VREF_IN UGATE C SS ISL6532B LGATE VTT VDDQ VTT VDDQ ...

  • Page 5

    Absolute Maximum Ratings 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V ...

  • Page 6

    Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) PARAMETER PWM CONTROLLER GATE DRIVERS UGATE and LGATE Source UGATE and LGATE Sink NCH BACKFEED CONTROL NCH Current Sink ...

  • Page 7

    LGATE (Pin 19) LGATE drives the lower (synchronous) FET of the V synchronous buck switching regulator. LGATE is driven between GND and P12V. FB (Pin 11) and COMP (Pin 12) The V switching regulator employs a single voltage DDQ control ...

  • Page 8

    ACPI State Transitions Cold Start (S5/ Transition) At the onset of a mechanical start, the ISL6532B receives it’s bias voltage from the 5V Standby bus (5VSBY). As soon as the SLP_S3 and SLP_S5 signals have transitioned HIGH, the ...

  • Page 9

    S3 S5 12VATX 2V/DIV 2048 CLOCK CYCLES 12V POR PGOOD COMPARATOR FIGURE 2. TYPICAL STATE TRANSITION V Over Current Protection TT The internal V LDO is protected from fault conditions TT through a 3.3A current limit. This ...

  • Page 10

    Careful component layout and printed circuit board design minimizes these voltage spikes example, consider the turn-off transition of the upper MOSFET. Prior to ...

  • Page 11

    DRIVER OSC PWM COMPARATOR - DRIVER ∆V + OSC E REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS COMP ISL6532B REFERENCE   ...

  • Page 12

    However, since the value of R1 affects the values of the rest of the compensation components advisable to keep its value less than 5kΩ. Depending on the value chosen for R1, R4 can be calculated based on the ...

  • Page 13

    The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the ...

  • Page 14

    ISL6532B Application Circuit Figure 7 shows an application circuit utilizing the ISL6532B. Detailed information on the circuit, including a complete Bill- +3. 10.0kΩ PGOOD DDQ REF 0.1µ 0.1µ ...

  • Page 15

    ... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...