ISL6532BCR Intersil, ISL6532BCR Datasheet - Page 8

IC REG/CTRLR ACPI DUAL DDR 20QFN

ISL6532BCR

Manufacturer Part Number
ISL6532BCR
Description
IC REG/CTRLR ACPI DUAL DDR 20QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6532BCR

Applications
Memory, DDR/DDR2 Regulator
Current - Supply
5.25mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Voltage - Supply
-
ACPI State Transitions
Cold Start (S5/S4 to S0 Transition)
At the onset of a mechanical start, the ISL6532B receives it’s
bias voltage from the 5V Standby bus (5VSBY). As soon as
the SLP_S3 and SLP_S5 signals have transitioned HIGH,
the ISL6532B starts an internal counter. Following a cold
start or any subsequent S5 state, state transitions are
ignored until the system enters S0/S1. None of the
regulators will begin the soft start procedure until the 5V
Standby bus has exceeded POR, the 12V bus has exceeded
POR and V
Once all of these conditions are met, the PWM error
amplifier will first be reset by internally shorting the COMP
pin to the FB pin. This reset lasts for 2048 clock cycles which
is typically 8.2ms (one clock cycle = 1/f
start sequence will then begin.
The PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). The
internal V
that tracks the output of the PWM regulator. The soft start
lasts for 2048 clock cycles, which is typically 8.2ms. This
method provides a rapid and controlled output voltage rise.
Figure 1 shows the soft start sequence for a typical cold
start. Due to the soft start capacitance, C
VREF_IN pin, the S5 to S0 transition profile of the V
will have a more rounded features at the start and end of the
soft start whereas the V
ending points to the ramp up.
S3
S5
TT
12V POR
NCH
LDO will also soft start through the reference
FIGURE 1. TYPICAL COLD START
2048 CLOCK
has exceeded the trip level.
CYCLES
5VSBY
1V/DIV
SOFT START
INITIATES
DDQ
12VATX 2V/DIV
profile has distinct starting and
2048 CLOCK
8
CYCLES
PGOOD COMPARATOR
SOFT START ENDS
OSC
ENABLED
SS
). The digital soft
, on the
500mV/DIV
500mV/DIV
PGOOD
5V/DIV
V
TT
V
DDQ
TT
rail
ISL6532B
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals, the ISL6532B can achieve PGOOD status
significantly faster than other devices that depend on the
Latched_Backfeed_Cut signal for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532B will disable the V
standby regulator will be enabled and the V
regulator will be disabled. NCH is pulled low to disable the
backfeed blocking MOSFET. PGOOD will also transition
LOW. When V
V
the V
rail will depend on the leakage characteristics of the memory
and MCH I/O pins. It is important to note that the V
may not bleed down to 0V.
The V
standby V
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4 and 8µs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6532B will enable the V
the V
the NCH pin to a high impedance state turning on the
blocking MOSFET. The internal short between the V
reference and the V
short, the capacitor on VREF_IN is then charged up through
the internal resistor divider network. The V
follow this capacitor charge-up, acting as the S3 to S0
transition soft start for the V
is enabled only after 2048 clock cycles, or typically 8.2ms,
have passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
should be noted that the soft start profile of the V
output will vary according to the value of the capacitor on the
VREF_IN pin.
Active to Shutdown (S0 to S4/S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6532B IC disables all
regulators and forces the PGOOD pin and the NCH pin
LOW.
TT
regulator is internally shorted to the V
TT
DDQ
DDQ
rail to float. When floating, the voltage on the V
DDQ
standby regulator, enable the V
rail will be supported in the S3 state through the
TT
LDO. When S3 transitions LOW, the Standby
is disabled, the internal reference for the
TT
rail is released. Upon release of the
DDQ
TT
TT
linear regulator. The V
rail. The PGOOD comparator
switching regulator, disable
TT
TT
TT
DDQ
rail. This allows
LDO and force
output will
switching
TT
TT
TT
LDO
DDQ
rail
TT

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