ISL6532CR Intersil, ISL6532CR Datasheet - Page 8

• Manufacturer Part Number: ISL6532CR
• Description: IC REG/CTRLR ACPI DUAL DDR 20QFN
• Manufacturer: Intersil

Specifications of ISL6532CR

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 5.25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -

the ISL6532 starts an internal counter. Following a cold start
or any subsequent S5 state, state transitions are ignored
until the system enters S0/S1. None of the regulators will
begin the soft start procedure until the 5V Standby bus has
exceeded POR, the 12V bus has exceeded POR and V
has exceeded the trip level.
Once all of these conditions are met, the PWM error
amplifier will first be reset by internally shorting the COMP
pin to the FB pin. This reset lasts for 2048 clock cycles which
is typically 8.2ms (one clock cycle = 1/f
start sequence will then begin.
The PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). The
internal V
tracks the output of the PWM regulator. The soft start lasts for
2048 clock cycles, which is typically 8.2ms. This method
provides a rapid and controlled output voltage rise.
Figure 1 shows the soft start sequence for a typical cold
start. Due to the soft start capacitance, C
VREF_IN pin, the S5 to S0 transition profile of the V
will have a more rounded features at the start and end of the
soft start whereas the V
ending points to the ramp up.
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals, the ISL6532 can achieve PGOOD status
significantly faster than other devices that depend on the
Latched_Backfeed_Cut signal for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532 will disable the V
standby regulator will be enabled and the V
regulator will be disabled. NCH is pulled low to disable the
S3
S5
TT
12V POR
LDO will also soft start through the reference that
FIGURE 1. TYPICAL COLD START
2048 CLOCK
CYCLES
5VSBY
1V/DIV
SOFT START
DDQ
INITIATES
TT
12VATX 2V/DIV
profile has distinct starting and
linear regulator. The V
8
2048 CLOCK
CYCLES
PGOOD COMPARATOR
SOFT START ENDS
OSC
ENABLED
SS
). The digital soft
DDQ
, on the
switching
500mV/DIV
500mV/DIV
DDQ
PGOOD
5V/DIV
TT
V
DDQ
V
TT
rail
NCH
ISL6532
backfeed blocking MOSFET. PGOOD will also transition
LOW. When V
V
the V
rail will depend on the leakage characteristics of the memory
and MCH I/O pins. It is important to note that the V
may not bleed down to 0V.
The V
standby V
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4 and 8µs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the ISL6532
will enable the V
standby regulator, enable the V
pin to a high impedance state turning on the blocking
MOSFET. The internal short between the V
the V
capacitor on VREF_IN is then charged up through the
internal resistor divider network. The V
this capacitor charge-up, acting as the S3 to S0 transition
soft start for the V
enabled only after 2048 clock cycles, or typically 8.2ms, have
passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
should be noted that the soft start profile of the V
output will vary according to the value of the capacitor on the
VREF_IN pin.
TT
S3
S5
regulator is internally shorted to the V
TT
TT
DDQ
FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION
rail to float. When floating, the voltage on the V
rail is released. Upon release of the short, the
DDQ
rail will be supported in the S3 state through the
TT
LDO. When S3 transitions LOW, the Standby
DDQ
12V POR
is disabled, the internal reference for the
TT
rail. The PGOOD comparator is
switching regulator, disable the V
2048 CLOCK
CYCLES
12VATX 2V/DIV
TT
PGOOD COMPARATOR
LDO and force the NCH
ENABLED
TT
TT
output will follow
TT
rail. This allows
reference and
500mV/DIV
500mV/DIV
PGOOD
TT
5V/DIV
V
V
DDQ
TT
TT
LDO
rail
DDQ
TT