IC REG/CTRLR ACPI DUAL DDR 28QFN

ISL6537CR

Manufacturer Part NumberISL6537CR
DescriptionIC REG/CTRLR ACPI DUAL DDR 28QFN
ManufacturerIntersil
ISL6537CR datasheet
 


Specifications of ISL6537CR

ApplicationsMemory, DDR/DDR2 RegulatorCurrent - Supply7mA
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case28-QFNLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Voltage - Supply-  
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Data Sheet
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
during S0/S1 and S3 states. During S0/S1
DDQ
state, a fully integrated sink-source regulator generates an
accurate (V
/2) high current V
voltage without the
DDQ
TT
need for a negative supply. A buffered version of the V
reference is provided as V
. Two LDO controllers are also
REF
integrated for the GMCH core voltage regulation and for the
GMCH and CPU V
termination voltage regulation.
TT
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±
2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V
TT
is within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Pinout
ISL6537 (6x6 QFN)
TOP VIEW
28
27
26
25
24
23
5VSBY
1
S3#
2
3
P12V
GND
GND
4
29
5
DDR_VTT
DDR_VTT
6
VDDQ
7
8
9
10
11
12
13
1
Features
• Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V
- LDO Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V
• ACPI Compliant Sleep State Control
/2
DDQ
• Glitch-free Transitions During State Changes
• Integrated V
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs:
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring on All Outputs
• OCP on the Switching Regulator
termination voltage
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI Compliant PCs
• Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
22
• DSP Supplies
21
DRIVE4
Ordering Information
20
REFADJ4
PART
19
DRIVE3
NUMBER
FB3
18
ISL6537CR
17
FB4
ISL6537CRZ
(See Note)
16
COMP
*Add “-T” suffix to part number for tape and reel packaging.
15
FB
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
14
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
All other trademarks mentioned are the property of their respective owners.
ISL6537
July 18, 2007
FN9142.6
Termination
TT
Buffer
REF
±
2% Over Temperature
PART
TEMP.
MARKING
RANGE (°C)
PACKAGE
ISL6537CR
0 to +70
28 Ld 6x6 QFN L28.6x6
ISL6537CRZ
0 to +70
28 Ld 6x6 QFN
(Pb-free)
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved
DDQ
TT
PKG.
DWG. #
L28.6x6

ISL6537CR Summary of contents

  • Page 1

    ... Over Temperature PART TEMP. MARKING RANGE (°C) PACKAGE ISL6537CR 6x6 QFN L28.6x6 ISL6537CRZ 6x6 QFN (Pb-free) | Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved DDQ TT PKG. DWG. # ...

  • Page 2

    Block Diagram VDDQ P12V R GU EA4 DRIVE4 GMCH DUAL LDO R GL FB4 REFADJ4 P12V EA3 DRIVE3 FB3 P12V EA2 DRIVE2 FB2 5VSBY P12V S3# S5# FB POR MONITOR AND CONTROL FAULT SOFT-START & ENABLE A SOFT-START & ENABLE ...

  • Page 3

    Simplified Power System Diagram V DDQ SLP_S3 SLP_S5 GMCH + Q5 V TT_GMCH/CPU + Typical Application V DDQ_DDR SLP_S5 SLP_S3 GMCH TT_GMCH/CPU 3 ISL6537 12V 5VSBY SLEEP STATE LOGIC PWM ...

  • Page 4

    ... Thermal Information Thermal Resistance QFN Package (Notes Maximum Junction Temperature (Plastic Package +150° 7.0V (DC) Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp SYMBOL TEST CONDITIONS I S3# and S5# HIGH, UGATE/LGATE Open CC_S0 I S5# LOW, S3# Don’t Care, UGATE/LGATE ...

  • Page 5

    Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) PARAMETER PWM CONTROLLER GATE DRIVERS UGATE and LGATE Source UGATE and LGATE Sink VTT REGULATOR Upper Divider Impedance Lower ...

  • Page 6

    Functional Pin Description 5VSBY (Pin 1) 5VSBY is the bias supply of the ISL6537 typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6537 enters a reduced power mode and ...

  • Page 7

    BOOT (Pin 25) This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-channel MOSFET. FB2 (Pin 11) Connect the output of the V ...

  • Page 8

    SLP_S3# SLP_S5# 12V POR 12V 0V V DDQ_DDR 0V V DDQ_DDR V TT_DDR 0V V GMCH_UPPER 0V V GMCH 0V V TT_GMCH/CPU 0V VIDPGD (3 SOFTSTART CYCLES Soft-Start Rise Time Dependent ...

  • Page 9

    The digital soft-start for the PWM regulator is accomplished by clamping the error amplifier reference input to a level proportional to the internal digital soft-start voltage. As the soft- start voltage slews up, the PWM comparator generates PHASE pulses of ...

  • Page 10

    Fault Counter reaches a count any other time. The 16384 counts that are required to reset the Fault Reset Counter represent 8 soft-start cycles, as one soft-start cycle is 2048 clock ...

  • Page 11

    Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit ...

  • Page 12

    DRIVER OSC PWM COMPARATOR - DRIVER ΔV + OSC E REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS COMP ISL6537 REFERENCE ⎛ ⎞ ...

  • Page 13

    The output voltage programming resistor will depend on the value chosen for the feedback resistor and the desired output voltage of the particular regulator. × ---------------------------------- - V 0.8V – DDQ × ...

  • Page 14

    Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSFET and the source of lower MOSFET. The important parameters for the bulk input capacitance are the voltage rating and the RMS ...

  • Page 15

    ... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...