ISL6537CR Intersil, ISL6537CR Datasheet - Page 12

• Manufacturer Part Number: ISL6537CR
• Description: IC REG/CTRLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6537CR

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6537) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F LC
1. Pick Gain (R
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
2. Place 1
ΔV
3
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
, C
OSC
=
FB
1
------------------------------------------ -
2π x
, C
V
. The goal of the compensation network is to provide
DDQ
OSC
2
ST
, and C
ND
ST
ND
0dB
L O x C O
COMPARATOR
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
=
1
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero.
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
ERROR
AMP
) and adequate phase margin. Phase margin
DETAILED COMPENSATION COMPONENTS
V
0.8
ISL6537
2
E/A
PWM
/R
3
×
) in Figure 5. Use these guidelines for
Z
+
1
-
⎛
⎜
⎝
FB
) for desired converter bandwidth.
-
+
COMP
1
C
REFERENCE
+
2
REFERENCE
R
------ -
R
C
1
4
-
+
1
⎞
⎟
⎠
12
DRIVER
DRIVER
R
F ESR
Z
2
IN
=
FB
Z
------------------------------------------- -
2π x ESR x C O
FB
PHASE
R
(PARASITIC)
V
C
4
IN
3
Z
L
R
1
O
IN
1
R
ESR
3
C
O
V
DDQ
0dB
(EQ. 4)
LC
1
V
, R
DDQ
and
IN
).
2
,
ISL6537
Compensation Break Frequency Equations
Figure 4 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 4. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 4 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 3.
F
F
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
0
and Z
=
=
----------------------------------- -
2π x R
------------------------------------------------------ -
2π x R
10
(R
20LOG
MODULATOR
2
IN
/R
(
1
1
to provide a stable, high bandwidth (BW) overall
GAIN
)
2
100
1
x C
+
1
R
1
3
) x C
1K
F
Z1
F
FREQUENCY (Hz)
3
LC
F
Z2
10K
F
F
F
P1
P2
F
P1
ESR
(V
=
=
100K
IN
20LOG
F
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
/ΔV
P2
OSC
P2
OPEN LOOP
ERROR AMP GAIN
1
1M
)
2
3
with the
x
x C
1
COMPENSATION
⎛
⎜
⎝
CLOSED LOOP
C
--------------------- -
C
3
1
1
10M
GAIN
+
x C
GAIN
July 18, 2007
C
2
2
(EQ. 5)
FN9142.6
⎞
⎟
⎠