L6740L STMicroelectronics, L6740L Datasheet
L6740L
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L6740L Summary of contents
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... AMD processors. The device embeds two independent control loops for the CPU core and the integrated NB, each one with its own set of protections. L6740L is able to work in single-plane mode, addressing only the CORE section, according to the parallel DAC codification. When in dual-plane mode ...
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... CORE section - load-line and load-indicator (optional 6.4 CORE section - offset (optional 6.5 NB section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6 NB section - load-line and load-indicator (optional 6.7 NB section - offset (optional 2/44 Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PSI_L and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 21 HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 L6740L ...
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... L6740L 6.8 NB section - maximum duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 On-the-fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.10 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.10.1 7 Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 31 7.1 Programmable overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4 Over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.1 7.4.2 8 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 LTB Technology™ ...
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... BOOT C HF_NB HS UGATE PHASE LS LGATE OUT_NB MLCC_NB (*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details (**) Pin not listed to be considered as Not Connected ST L6740L (4+1) Reference Schematic 4/44 48 PWM1 47 PWM2 46 PWM3 45 PWM4 44 NB_PWM 21 R OC_TH OC_PHASE 28 R OC_AVG ...
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... UGATE PHASE LS LGATE OUT_NB MLCC_NB (*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details (**) Pin not listed to be considered as Not Connected ST L6740L (3+1) Reference Schematic Typical application circuit and block diagram 48 PWM1 47 PWM2 46 PWM3 45 PWM4 44 NB_PWM 21 R OC_TH ...
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... BOOT C HF_NB HS UGATE PHASE LS LGATE OUT_NB MLCC_NB (*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details (**) Pin not listed to be considered as Not Connected ST L6740L (2+1) Reference Schematic 6/44 48 PWM1 47 PWM2 46 PWM3 45 PWM4 44 NB_PWM 21 R OC_TH OC_PHASE 28 R OC_AVG ...
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... PWM4 Σ PWM4 OSC OSC 1.24V VCC VCC SGND OFFSET SGND Typical application circuit and block diagram INTERFACE CORE_REF & NB_REF ENDRV NB_ENDRV L6740L OSC CONTROL LOGIC OUTPUT VOLTAGE MONITOR AND PROTECTION MANAGEMENT CS1- CORE - TOT CURRENT I DROOP 64k REMOTE ERROR ...
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... It manages OVP and UVP protections and PWRGOOD. Connect to the positive side of the load for remote sensing. See 24 N.C. 23 NB_ISEN 22 N.C. 21 OC_PHASE 20 CS4- 19 CS4+ 18 CS3- 17 CS3+ 16 CS2- 15 CS2+ 14 CS1- 13 CS1 Function to FB. The CORE section or the device cannot F to VSEN and with Section 7 L6740L to COMP. for details. ...
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... L6740L Table 2. Pin description (continued) Pin# Name OVP / V_FIX 11 LTB_GAIN 12 PSI_L Pins description and connection diagrams Remote ground sense. FBG Connect to the negative side of the load for remote sensing. See Section 9 for proper layout of this connection. Offset programming pin. Internally set to 1.24 V. Connecting a R ...
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... CS4+. G Section 7.4.1 Section 7.4 for details. SW for details). If floating, the switching = 2.5 V Typ) the device latches with all mosfets resistor to SGND allows OS_NB . Short to SGND to FB_NB Section 6.7 for details. L6740L resistor G it OC_TH for details. of both Section 7 for ...
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... L6740L Table 2. Pin description (continued) Pin# Name 31 NB_VSEN 32 NB_DROOP 33 NB_FB 34 NB_COMP 35, VID0, VID1 36 37 PWROK 38 39 SVC / VID3 40 SVD / VID2 41 PWRGOOD Pins description and connection diagrams NB output voltage monitor. It manages OVP and UVP protections and PWRGOOD. Connect to the positive side of the NB load to perform remote sensing. See for proper layout of this connection ...
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... By shorting to SGND PWM4 or PWM3 and PWM4 possible to program the CORE section to work phase respectively. See Section 5.4.4 for details about HiZ management. Thermal pad connects the silicon substrate and makes good thermal contact with the PCB. Connect to the PGND plane. Parameter L6740L Value Unit 40 °C/W 1 °C/W 150 ° ...
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... L6740L 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V to PGND CC All other pins to PGNDx 3.2 Electrical characteristics Table 5. Electrical characteristics ( ± 15 Symbol Parameter Supply current and power-ON I VCC supply current CC VCC turn-ON UVLO VCC VCC turn-OFF Oscillator ...
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... L6740L Unit μA % μA μA dB V/μ μ μ μA μ μA μA ...
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... SVI communication. It embeds two independent controllers for CPU CORE and the integrated NB, each one with its own set of protections. L6740L is able to detect which kind of CPU is connected in order to configure itself to work as a single-plane PVI controller or dual-plane SVI controller. The controller performs a single-phase control for the NB section and a programmable 2-to- ...
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... At system start-up, on the rising-edge of the EN signal, the device monitors the status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0). When in PVI mode, L6740L uses the information available on the VID[0: 5] bus to address the CORE section output voltage according to ...
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... L6740L Table 6. Voltage identifications (VID) codes for PVI mode VID5 VID4 VID3 VID2 VID1 VID0 Hybrid CPU support and CPU_TYPE detection Output VID5 VID4 VID3 VID2 VID1 VID0 voltage 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 ...
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... SVI start-up Once the SVI mode has been detected on the EN rising-edge, L6740L checks for the status of the two serial VID pins, SVC and SVD, and stores this value as the Pre-PWROK Metal VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes to the voltage level prescribed by the Pre-PWROK Metal VID ...
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... Refer to L6740L is able to manage individual power OFF for both the sections. The CPU may issue a serial VID command to power OFF or power ON one section while the other one remains powered. In this case, the PWRGOOD signal remains asserted. ...
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... L6740L Output Output SVI [6:0] voltage voltage 0.7500 110_0000 0.3500 0.7375 110_0001 0.3375 0.7250 110_0010 0.3250 0.7125 110_0011 0.3125 0.7000 110_0100 ...
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... L6740L 5.4.2 PWROK de-assertion Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored Pre-PWROK Metal VID and regulates all the planes to that level performing an On-the-Fly transition to that level. PWRGOOD is treated appropriately being de-asserted in case the Pre-PWROK Metal VID voltage is out of the initial voltage specifications ...
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... System efficiency enhancement by PSI 5.4.4 HiZ management L6740L is able to manage HiZ through both the PWMx and driver enable signals. When the controller wants to set in high impedance the output of one section, it set the relative PWM floating and, at the same time, pulls-low the related ENDRV. ...
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... L6740L embeds a dual remote-sense buffer to sense remotely the regulated voltage of each section without any additional external components. In this way, the output voltage programmed is regulated compensating for board and socket losses. Keeping the sense traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise ...
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... CORE section - current reading and current sharing loop L6740L embeds a flexible, fully-differential current sense circuitry for the CORE section that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy ...
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... CORE section - load-line and load-indicator (optional) L6740L is able to introduce a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current ...
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... FB pin and the regulated voltage. 6.5 NB section - current reading L6740L embeds a flexible, fully-differential current sense circuitry for the NB section that is able to read across low-side MOSFET R the element. The trans-conductance ratio is issued by the external resistor R outside the chip between NB_ISEN pin and the low-side drain. The current sense circuit performs sample and hold of the current information ...
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... L6740L 6.6 NB section - load-line and load-indicator (optional) This method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a depen- dence of the output voltage on the load current, a static error, proportional to the output cur- rent, causes the output voltage to vary according to the sensed current ...
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... On-the-fly VID transitions L6740L manages on-the-fly VID transitions that allow the output voltage of both sections to modify during normal device operation for CPU power management purposes. OV, UV and PWRGOOD signals are masked during every OTF-VID Transition and they are re-activated with a 16 clock cycle delay to prevent from false triggering ...
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... EN is asserted. ● V_FIX mode. L6740L checks for SVC/SVD modifications and, once the new code is stable, it steps the reference of both sections up or down according to the target-VID with a 3 mV/μsec. slope (Typ). until the new VID code is reached. OV, UV and PWRGOOD are masked during the transition and re-activated with a 16 clock cycle delay after the end of the transition to prevent from false triggering ...
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... LS-Less start-up In order to avoid any kind of negative undershoot on the load side during start-up, L6740L performs a special sequence in enabling the drivers for both sections: during the soft-start phase, the LS MOSFET is kept OFF (PWMx set to HiZ and ENDRVx = 0) until the first PWM pulse. After the first PWM pulse, the PWMx outputs switches between logic “ ...
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... Over-current (OC) On-the-fly VID 7.1 Programmable overvoltage Once VCC crosses the turn-ON threshold and the device is enabled (EN = 1), L6740L pro- vides an overvoltage protection for both the sections: when the voltage sensed by VSEN and/or NB_VSEN overcomes the OV threshold, the controller: – Permanently sets the PWM of the involved section to zero keeping ENDRV of that section high in order to keep all the low-side MOSFETs on to protect the load of the section in OV condition ...
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... Filter OVP pin with 100 pF(max) to SGND. 7.2 Feedback disconnection L6740L provides both CORE and NB sections with FB Disconnection protection. This fea- ture acts in order to stop the device from regulating dangerous voltages in case the remote sense connections are left floating. The protection is available for both the sections and operates for both the positive and negative sense ...
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... OC. 7.4.1 CORE section L6740L performs two different OC protections for the CORE section: it monitors both the average current and the per-phase current and allows to set an OC threshold for both. – OC_PHASE pin allows to define a maximum information current per-phase (I ) ...
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... Low-Side ON ) according to system OC_AVGmax = 33 kΩ (OC_PHASE pin is fixed to ). OC_TH = I when I is about 10% higher OC_TH OUT OC_AVGTH is the AVG_OC threshold OC_AVGmax can be considered to add a delay in OC_TH ISEN skipping clock cycles. The high-side L6740L G at the to < OC_TH overcomes ISEN ...
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... L6740L rent operation since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the I dition is when the ON time reaches its maximum value (see pens, the section works in real constant current and the output voltage decrease as the load increase ...
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... Connecting R OSC according to the following relationships 150kHz + SW Figure 15. R OSC 36/44 Figure 15). to SGND the frequency is increased (current is sunk from the pin), 1.240V kHz ⋅ --------------------------- - 6.8 ---------- - = 150kHz + ( ) μA R kΩ OSC vs. switching frequency OSC 6 ⋅ 8.432 10 ---------------------------- - ( ) R kΩ OSC L6740L ) typically ...
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... L6740L 9 System control loop compensation The device embeds two separate and independent control loops for CORE and NB section. The control loop for NB section is a simple voltage-mode control loop with (optional) voltage positioning featured when DROOP pin is shorted with FB. The control loop for the CORE section also features a current-sharing loop to equalize the current carried by each of the configured phases ...
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... minimum (0) value. The output voltage MAX (while it is charged by d OUT (s) LOOP ω ω ω ESR ( correspondence with the ω and imposing the cross might be not higher than during a load MAX IN OUT L6740L Z (s) F ω ω T ...
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... L6740L 10 LTB Technology™ LTB Technology™ further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immediately turning ON all the phases to provide the correct amount of energy to the load. By properly designing the LTB network as well as the LTB gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count. LTB Technology™ ...
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... LTBGAIN pin and I Design Tips. to increase the system sensitivity making the system sensitive to LTB . OUT to increase the system sensitivity making the system sensitive to LTB to increase the width of the LTB pulse reducing the system LTBGAIN L6740L is the OSC current OSC ...
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... The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Since L6740L uses external drivers to switch the power MOSFETs, check the selected driver documentation for informations related to proper layout for this part. ...
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... Body 1.0mm 0.217 0.019 0.75 0.018 0.024 0.030 0.039 0.08 0.0031 OUTLINE AND MECHANICAL DATA TQFP48 - EXPOSED PAD 7222746 B L6740L ...
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... L6740L 13 Revision history Table 13. Document revision history Date 07-Jun-2007 01-Aug-2007 22-Sep-2008 Revision 1 First release 2 Databrief updated to datasheet 3 Updated coverpage Revision history Changes 43/44 ...
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