ISL6505CB-T Intersil, ISL6505CB-T Datasheet

no-image

ISL6505CB-T

Manufacturer Part Number
ISL6505CB-T
Description
IC MULTIPLE POWER CTRLR 20-SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6505CB-T

Applications
Power Supply Controller/Monitor
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
6mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Voltage - Input
-
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6505 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates three linear controllers/regulators, switching,
monitoring and control functions into a 20-pin wide-body
SOIC or 20-pin QFN (also known as MLF) 5x5 package.
The ISL6505’s operating mode (active or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3V
voltage plane from the ATX supply’s 5V
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3V
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses. The 3.3V
output is active for as long as the ATX 5V
to the chip.
A controller powers up the 5V
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5V
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6505 5V
based on the state of the EN5 pin.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element.
A linear controller generates V
3.3V
The voltage is user-programmable to values between 1.2V
and 1.5V, using an external resistor divider. The mode is
user-selectable with the LAN pin; a logic high (or open)
selects the 10/100 LAN mode, where V
(S0-S5); a logic low selects the Gigabit Ethernet mode,
where V
DUAL
OUT1
/3.3V
DUAL
is only on during active modes (S0-S2).
SB
output is either shut down or stays on,
voltage plane, using an external NFET.
®
SB
DUAL
1
OUT1
through a PMOS (or PNP)
plane by switching in the
Data Sheet
from the
DUAL
OUT1
SB
SB
DUAL
output, powering
voltage is applied
/3.3V
is always on
/3.3V
DUAL
SB
SB
linear
/3.3V
1-888-INTERSIL or 1-888-468-3774
SB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Provides four ACPI-Controlled Voltages
• Excellent Output Voltage Regulation
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
• QFN Package:
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• ACPI-Compliant Power Regulation for Motherboards
Ordering Information
Add “-T” suffix for tape and reel.
NOTE:
Pinouts
ISL6505CB*
ISL6505CR*
ISL6505CRZ*
(Note 1)
ISL6505EVAL1
ISL6505EVAL2
PART NUMBER
1. Intersil Pb-free plus anneal products employ special Pb-free
- 5V
- 3.3V
- 1.2V
- V
- All Outputs: ±2.0% over temperature (as applicable)
FAULT Reporting and Temperature Shutdown
- Compliant to JEDEC PUB95 MO-220
- Near Chip Scale Package footprint, which improves
December 1, 2005
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
QFN - Quad Flat No Leads - Package Outline
PCB efficiency and has a thinner profile
OUT1
DUAL
All other trademarks mentioned are the property of their respective owners.
DUAL
VID
|
- See page 6.
(1.2V - 1.5V programmable) LAN/Ethernet
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Processor VID Circuitry
USB/Keyboard/Mouse
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved
/3.3V
Evaluation Board (SOIC)
Evaluation Board (QFN)
RANGE (°C)
0 to 70
0 to 70
0 to 70
TEMP.
SB
PCI/Auxiliary/LAN
20 Ld Wide SOIC
20 Ld 5x5 QFN
20 Ld 5x5 QFN
(Pb-free)
PACKAGE
ISL6505
FN9109.3
M20.3
L20.5x5
L20.5x5
DWG. #
PKG.

Related parts for ISL6505CB-T

ISL6505CB-T Summary of contents

Page 1

... SB • Pb-Free Plus Anneal Available (RoHS Compliant) voltage is applied SB Applications • ACPI-Compliant Power Regulation for Motherboards Ordering Information PART NUMBER ISL6505CB* ISL6505CR* ISL6505CRZ* (Note 1) ISL6505EVAL1 ISL6505EVAL2 Add “-T” suffix for tape and reel. NOTE: 1. Intersil Pb-free plus anneal products employ special Pb-free ...

Page 2

Block Diagram 3V3DLSB EA3 + DR1 - TO UV DETECTOR FB1 FAULT UV DETECTOR UV COMP 4.10V 5VDL GND 3V3DL 5V 3V3 EA4 - + 4.4V/3.4V 3V3 MONITOR 5V MONITOR 2.75V/2.60V 4.5V/4.25V MONITOR AND CONTROL + 10 µ A 0.80V ...

Page 3

Simplified Power System Diagram +5V IN +12V IN +5V SB +3.3V IN FAULT Q2 Q3 3.3V /3.3V DUAL SB 3. OUT1 R21 SHUTDOWN SX, EN5, LAN 4 Typical Application +5V IN +12V IN +5V SB +3. ...

Page 4

Absolute Maximum Ratings Supply Voltage +7.0V 5VSB DLA . ...

Page 5

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) PARAMETER 1.2V LINEAR REGULATOR (V ) VID OUT2 1V2VID Regulation 1V2VID Nominal Voltage Level 1V2VID Undervoltage Rising Threshold 1V2VID Undervoltage Hysteresis 1V2VID Output Current ...

Page 6

Pinouts ISL6505 (20 LEAD WIDE SOIC) TOP VIEW 1 FB1 DR1 2 3V3DLSB 3 3V3DL 4 1V2VID 5 3V3 EN5 Functional Pin Description (Pin numbers for SOIC and QFN) 3V3 (Pin 6 ...

Page 7

SS (Pin 17 SOIC; Pin 14 QFN) Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1µF recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ...

Page 8

The internal circuitry does not allow the transition from an S4/S5 (suspend to disk/soft off) state (suspend to RAM) state; however, it does allow the transition from S3 to S4/S5. The only ‘legal’ transitions are from an ...

Page 9

Soft-Start into Sleep States (S3, S4/S5) The 5V POR function initiates the soft-start sequence internal 10µA current source charges an external capacitor. The error amplifiers’ reference inputs are clamped to a level proportional to the SS (soft-start) pin ...

Page 10

V DUAL SB OUT1 up right after bias voltage surpasses POR level (but if LAN = GND, then V output will not come up until the soft-start OUT1 ramp, along with V ; see Figure 9). ...

Page 11

Application Guidelines Soft-Start Interval The 5V output of a typical ATX supply is capable of SB 725mA, with newer models rated for 1.0A, and even 2.0A. During power- sleep state, the 5V needs to provide sufficient current to ...

Page 12

Since the pin can nominally sink 1.2mA with only a 0.1V drop, a 1kΩ resistor will match that condition. The minimum input low logic level is typically around 25-30% of the 1.2V supply (0.3V in this example), and the ...

Page 13

Layout Considerations The typical application employing an ISL6505 is a fairly straight forward implementation. Like with any other linear regulator, attention has to be paid to the few potentially sensitive small signal components, such as those connected to sensitive nodes ...

Page 14

The output voltage drop is heavily dependent on the ESR (equivalent series resistance) of the output capacitor bank, the choice of capacitors should be such as to maintain the output voltage above the lowest allowable regulation level. Input Capacitors Selection ...

Page 15

... Q4 can also be a PNP transistor, such as an MMBT2907AL. For additional, more detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN1053. Also see Intersil Corporation’s web page (www.intersil.com). Q6 3V3 5V ...

Page 16

... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the " ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Related keywords