ISL6595DRZ-TK Intersil, ISL6595DRZ-TK Datasheet
ISL6595DRZ-TK
Specifications of ISL6595DRZ-TK
Related parts for ISL6595DRZ-TK
ISL6595DRZ-TK Summary of contents
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... PART RANGE (Note) MARKING (°C) ISL6595DRZ* ISL6595 DRZ 7x7 QFN L48.7x7P *Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach ...
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Pinout 48 1 VID7 VID6 2 VID5 3 VID4 4 VID3 5 VID2 6 VID1 7 VID0 8 VID_SEL 9 LL1 10 OUTEN 11 VDD ISL6595 ISL6595 (48 LD QFN) TOP VIEW ...
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Functional Block Diagram (Differential I-Sense Inputs) VSENP VSENN RESET_N POR ISEN6+ ISEN6- ISEN5+ ISEN5- ISEN4+ ISEN4- CURRENT SENSE ISEN3+ ISEN3- ISEN2+ ISEN2- ISEN1+ ISEN1- TEMP TEMP_SEN SENSE V12_SEN SCL 2 SDA I C INTERNAL MEMORY SADDR OUTEN VID7 VID6 VID5 ...
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Typical VRD Application +12V +5V +3.3V VDD V12_SEN ISL6595 GND VID7 PWM1 VID6 ISEN1+ VID5 ISEN1- VID4 PWM2 VID3 ISEN2+ VID2 ISEN2- FROM µP VID1 PWM3 VID0 ISEN3+ VID_SEL ISEN3- LL1 PWM4 LL0 ISEN4+ OUTEN ISEN4- PWM5 TO µP VR_READY ...
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... Ld QFN Package Maximum Junction Temperature (Plastic Package) . 0°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +3.60V Operating Case Temperature . . . . . . . . . . . . . . . . . . 0°C to +125°C Operating Ambient Temperature . . . . . . . . . . . . . . . . . 0° ...
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Electrical Specifications V = +3.3V +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested (Continued) PARAMETER Bandwidth VSENP VSENN ISEN[6:1]+ INPUTS Input Current Range Input Resistance Clamp Voltage I-sense Amplifier Linearity Error ...
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Electrical Specifications V = +3.3V +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested (Continued) PARAMETER PWM[6:1] OUTPUTS Output LOW Voltage Output LOW Voltage FAULT1, FAULT2 OUTPUTS Output LOW Voltage Output LOW ...
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Pin Description PIN # NAME I/O 1 VID7 I 1.2V CMOS 2 VID6 I 1.2V CMOS 3 VID5 I 1.2V CMOS 4 VID4 I 1.2V CMOS 5 VID3 I 1.2V CMOS 6 VID2 I 1.2V CMOS 7 VID1 I 1.2V ...
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Pin Description (Continued) PIN # NAME I/O 34 ISEN2 ISEN2+ I Analog 36 VDD I VDD 37 PWM2 O 3.3V CMOS 38 ISEN1 ISEN1+ I Analog 40 PWM1 O 3.3V CMOS 41 CAL_CUR_SEN I Analog 42 ...
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... I C serial interface. The Intersil PowerCode interface allows full accessibility to regulator telemetry during system operation including: • Internal Controller Temperature • External (via optional thermistor) System Temperature • Per Phase Current • ...
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FET r , parasitic inductance and resistance by regulating to DS(ON) a low voltage level, putting a known current load through each phase individually and compensating for the current sense gain and offset error, ...
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ISL6595. These are single-ended r sense of the low-side FET, differential r low-side FET, or differential DCR sense of the buck inductor. The sensed current is digitized using a multiplexed current ADC. For low-side r current sense ...
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External Temperature Sense VIN PWM ISL6594 ISL6595 ISEN- PWM ADC FIGURE 4. DIFFERENTIAL DCR SENSE When configured to sense temperature from an external thermistor, the temperature sense input, TEMP_SEN, is set at virtual ground with a fixed offset of 300mV. ...
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TABLE 1. Intel VID VID VOLTAGE HI LO (HEX) (HEX) ( 1.60000 2 A 1.59375 2 D 1.5875 2 C 1.58125 2 F 1.57500 2 E 1.56875 3 1 1.56250 3 0 1.55625 3 3 1.55000 3 2 ...
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TABLE 1. Intel VID VID VOLTAGE HI LO (HEX) (HEX) ( 1.36875 5 1 1.36250 5 0 1.35625 5 3 1.35000 5 2 1.34375 5 5 1.33750 NOTE: 7. VID = (VID4, VID3, VID2), VID = (VID1, VID0, ...
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TABLE 2. Intel VR10 VID TABLE (8-BIT, Note 8) VID VID VOLTAGE VID (HEX) (HEX) (V) (HEX OFF OFF 1.60000 1.59375 1.58750 ...
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TABLE 2. Intel VR10 VID TABLE (8-BIT, Note 8) (Continued) VID VID VOLTAGE VID (HEX) (HEX) (V) (HEX 0.82500 0.81875 0.81250 0.80625 ...
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... If the input signal is three-state, the driver does not turn either high-side or low-side switches on and the power stage is high impedance or three-stated. Intersil’s ISL6594A, ISL6594B and ISL6596 FET drivers are optimized to operate with the ISL6595. ...
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For latched shutdown, user intervention to clear the latched fault is required before a new soft-start can be attempted. User intervention must come in the form of VR_EN toggle, RESET_N toggle, or controller power cycle. In addition to fault reporting, ...
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The ISL6595 will respond with the MS-byte at the current address. The master will respond with an Acknowledge to indicate to the ISL6595 that the transaction is not yet complete. The master again sends 8-clocks ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L48.7x7P 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 7/08 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW (4.00) sq (2.00) typ 4X (5.50) 4X (6.80) 48X (0.23) TYPICAL RECOMMENDED LAND PATTERN 22 ISL6595 ...