ADT7476ARQZ ON Semiconductor, ADT7476ARQZ Datasheet - Page 39

IC REMOTE THERMAL CTRLR 24QSOP

ADT7476ARQZ

Manufacturer Part Number
ADT7476ARQZ
Description
IC REMOTE THERMAL CTRLR 24QSOP
Manufacturer
ON Semiconductor
Series
dBCool®r
Datasheet

Specifications of ADT7476ARQZ

Function
Fan Control, Temp Monitor
Topology
ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
Sensor Type
External & Internal
Sensing Temperature
-40°C ~ 125°C, External Sensor
Output Type
SMBus™
Output Alarm
No
Output Fan
Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-QSOP
Full Temp Accuracy
+/- 0.5 C
Digital Output - Bus Interface
Serial (3-Wire, 4-Wire)
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Step 4—PWM
fan in the system runs. It is also the start speed for each fan
under automatic fan control once the temperature rises
above T
PWM
fan used, the PWM
duty cycle range. This value can be found through fan
validation.
single temperature measurement channel. For example,
Remote 1 temperature can control PWM1 and PWM2
outputs. If two different fans are used on PWM1 and PWM2,
the fan characteristics can be set up differently. As a result,
Fan 1 driven by PWM1 can have a different PWM
than that of Fan 2 connected to PWM2. Figure 55 illustrates
this as PWM1
minimum duty cycle of 20%, while PWM2
turns on at a minimum of 40% duty cycle. Note: Both fans
turn on at exactly the same temperature, defined by T
Programming the PWM Minimum Duty Cycle Registers
registers that allow the minimum PWM duty cycle for each
output to be configured anywhere from 0% to 100%. This
allows the minimum PWM duty cycle to be set in steps of
0.39%.
PWM
More than one PWM output can be controlled from a
The PWM minimum duty cycle registers are 8−bit
Figure 55. Operating Two Different Fans from a
Figure 54. PWM
MIN
PWM2
PWM1
PWM
MIN
MIN
100%
should be as low as possible. Depending on the
100%
MIN
0%
MIN
MIN
0%
is the minimum PWM duty cycle at which each
. For maximum system acoustic benefit,
Single Temperature Channel
MIN
MIN
for Each PWM (Fan) Output
MIN
T
(front fan), which is turned on at a
T
MIN
MIN
MIN
setting is usually in the 20% to 33%
Duty Cycle
Determines Minimum PWM
PWM2
PWM1
TEMPERATURE
TEMPERATURE
MIN
MIN
(rear fan)
http://onsemi.com
value
MIN
.
39
given by:
Example 1: For a minimum PWM duty cycle of 50%,
Example 2: For a minimum PWM duty cycle of 33%,
PWM Minimum Duty Cycle Registers
Register 0x64, PWM1 Minimum Duty Cycle = 0x80
(50% default)
Register 0x65, PWM2 Minimum Duty Cycle = 0x80
(50% default)
Register 0x66, PWM3 Minimum Duty Cycle = 0x80
(50% default)
Note on Fan Speed and PWM Duty Cycle
speed in RPM. Running a fan at 33% PWM duty cycle does
not equate to running the fan at 33% speed. Driving a fan at
33% PWM duty cycle actually runs the fan at closer to 50%
of its full speed. This is because fan speed in %RPM
generally relates to the square root of PWM duty cycle.
Given a PWM square wave as the drive signal, fan speed in
RPM approximates to:
Step 5—PWM
system runs at under the automatic fan speed control loop.
For maximum system acoustic benefit, PWM
as low as possible but should be capable of maintaining the
processor temperature limit at an acceptable level. If the
THERM temperature limit is exceeded, the fans are still
boosted to 100% for fail−safe cooling.
default value of this register is 0xFF and has no effect unless
it is programmed.
Figure 56. PWM
The value to be programmed into the PWM
The PWM duty cycle does not directly correlate to fan
PWM
There is a PWM
Value (decimal) = PWM
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) l or 54 (hex)
% fanspeed + PWM Duty Cycle
Cycle Below the THERM Temperature Limit
PWM
MAX
PWM
100%
MAX
MIN
0%
is the maximum duty cycle that each fan in the
MAX
MAX
for PWM (Fan) Outputs
MAX
T
MIN
Determines Maximum PWM Duty
limit for each fan channel. The
MIN
/0.39
TEMPERATURE
10
MAX
MIN
register is
should be
(eq. 5)

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