STTS424E02BDN3F STMicroelectronics, STTS424E02BDN3F Datasheet
STTS424E02BDN3F
Specifications of STTS424E02BDN3F
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STTS424E02BDN3F Summary of contents
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Features ■ STTS424E02 includes a JEDEC JC 42.4 compatible temperature sensor, integrated with industry standard 2 Kb serial presence detect (SPD) EEPROM (STTS2002 is recommended for new designs) Temperature sensor ■ Temperature sensor resolution: 0.25 °C (typ)/LSB ■ Temperature sensor ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STTS424E02 5 SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STTS424E02 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STTS424E02 is targeted for DIMM modules in mobile personal computing platforms (laptops), server memory modules and other industrial applications. The thermal sensor (TS) in the STTS424E02 is compliant with the JEDEC specification JC 42.4, which defines ...
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STTS424E02 2 Serial communications The STTS424E02 has a simple 2-wire SMBus™/I which allows the user to access both the 2 Kb serial EEPROM and the data in the temperature register at any time. It communicates via the serial interface with ...
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Serial communications Figure 1. Logic diagram 1. SDA and EVENT are open drain. Table 1. Signal names Pin Symbol SDA 6 SCL 7 EVENT SDA and ...
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STTS424E02 Figure 3. Block diagram 2Kb SPD EEPROM Software Write Protect Temperature Sensor Logic Control Comparator Timing ADC Capability Register Configuration Register Temperature Register Address ...
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Serial communications 2.2 Pin descriptions 2.2.1 A0, A1, A2 A2, A1, and A0 are selectable address pins for the 3 LSBs of the I They can be set to V internally connected to the E2, E1, E0 (chip selects) of ...
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STTS424E02 3 Temperature sensor operation The temperature sensor continuously monitors the ambient temperature and updates the temperature data register at least eight times per second. Temperature data is latched internally by the device and may be read by software from ...
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Temperature sensor operation 2 Figure 4. SMBus/I C write to pointer register 1 SCL SDA 0 0 Start by Master 2 Figure 5. SMBus/I C write to pointer register, followed by a read data word 1 SCL SDA 0 0 ...
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STTS424E02 Figure 6. SMBus/I SCL SDA Start by Master SCL (continued) SDA (continued) 2 3.2 SMBus/I C slave sub-address decoding The physical address for the TS is different than that used by the EEPROM. The TS physical address is binary ...
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Temperature sensor operation 2 3.3 SMBus timing consideration In order for this device to be both SMBus- and I each specification. The requirements which enable this device to co-exist with devices on either an SMBus ...
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STTS424E02 Table 2. AC SMBus and I Symbol t Bus free time between stop (P) and start (S) conditions BUF Hold time after (repeated) start condition. After this t HD:STA period, the first clock cycle is generated. (1) t Repeated ...
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Temperature sensor registers 4 Temperature sensor registers The temperature sensor component is comprised of various user-programmable registers. These registers are required to write their corresponding addresses to the pointer register. They can be accessed by writing to their respective addresses ...
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STTS424E02 Table 5. Pointer register select bits (type, width, and default values Name CAPA Thermal sensor capabilities CONF Configuration UPPER Alarm temperature upper boundary LOWER ...
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Temperature sensor registers Table 6. Capability register format Bit15 Bit14 RFU RFU Bit7 Bit6 RFU RFU Table 7. Capability register bit definitions Bit Basic capability 0 – Alarm and critical trips turned OFF. – Alarm and ...
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STTS424E02 4.2 Configuration register (read/write) The 16-bit configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and JEDEC requirements (see Table 8 on page 19 4.2.1 Event thresholds All ...
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Temperature sensor registers Table 9. Configuration register bit definitions Bit Event mode 0 – Comparator output mode (this is the default). – Interrupt mode; when either of the lock bits is set, this bit cannot be ...
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STTS424E02 Table 9. Configuration register bit definitions Bit Hysteresis enable (see Figure 8 – Hysteresis is disabled (this is the default). – Hysteresis is enabled at 1.5 °C. – Hysteresis is enabled at 3 ...
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Temperature sensor registers 4.2.5 Event output pin functionality The event outputs can be programmed to be configured as either a comparator output interrupt. This is done by enabling the output control bit (bit 3) and setting the ...
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STTS424E02 Figure 9. Event output boundary timings T CRIT T UPPER LOWER Comparator Interrupt S/W Int. Clear Critical Table 11. Legend for Note Event output boundary conditions When ...
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Temperature sensor registers 4.3 Temperature register (read-only) This 16-bit, read-only register stores the temperature measured by the internal band gap TS as shown in Table requirement. When reading this register, the MSBs (bit 15 to bit 8) are read first, ...
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STTS424E02 4.4 Temperature trip point registers (R/W) The STTS424E02 alarm mode registers provide for 11-bit data in 2s compliment format. The data provides for one LSB = 0.25 °C. All unused bits in these registers are read as '0'. The ...
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... Temperature sensor registers 4.5 Manufacturer ID register (read-only) The manufacturer’s ID (programmed value 104Ah) in this register is the STMicroelectronics identification provided by the Peripheral Component Interconnect Special Interest Group (PCiSIG). Table 18. Manufacturer ID register format Bit15 Bit14 0 0 Bit7 Bit6 0 1 4.6 Device ID and device revision ID register (read-only) The device IDs and device revision IDs are maintained in this register ...
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STTS424E02 5 SPD EEPROM operation 5 SPD EEPROM operation The 2 Kb serial EEPROM is able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use ...
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SPD EEPROM operation Prior to selecting the memory and issuing instructions, a valid and stable V be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until ...
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STTS424E02 Table 21. Operating modes Mode Current address read Random address read Sequential read Byte write Page write TS write TS read Figure 10. Result of setting the write protection Memory Area 5.4 Setting the write protection The Write Control ...
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SPD EEPROM operation 5.4.1 SWP and CWP If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a byte ...
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STTS424E02 5.5.1 Byte write After the device select code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoACK, and the location is ...
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SPD EEPROM operation 5.5.3 Write cycle polling using ACK During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum write time ...
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STTS424E02 5.6 Read operations - SPD Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read. Figure 14. Read mode ...
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SPD EEPROM operation 5.6.2 Current address read - SPD For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and ...
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STTS424E02 Table 23. Acknowledge when reading the write protection (instructions with R/W bit=1) Status Instruction Permanently PSWP, SWP or CWP protected SWP Protected with CWP SWP PSWP Not protected PSWP, SWP or CWP 5.7 Initial delivery state - SPD The ...
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Use in a memory module 6 Use in a memory module In the dual inline memory module (DIMM) application, the SPD is soldered directly on to the printed circuit module. The three chip enable inputs (A0, A1, A2) must be ...
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STTS424E02 7 Maximum ratings Stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
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DC and AC parameters 8 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the dc and ac characteristics tables that follow, are derived from tests ...
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STTS424E02 Table 27. DC/AC characteristics - temperature sensor component with EEPROM (continued) Sym Description (3) V Power on reset (POR) threshold POR Accuracy for corresponding range (4) C-grade 2.7 V ≤ V ≤ 3 Accuracy for corresponding range ...
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Package mechanical data 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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STTS424E02 Figure 15. DFN8 – 8-lead dual flat, no-lead ( mm) package outline (DA) 1. Drawing is not to scale. Table 28. DFN8 – 8-lead dual flat, no-lead ( mm) mechanical data (DA) Sym ...
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Package mechanical data Figure 16. TDFN8 – 8-lead thin dual flat, no-lead ( mm) package outline (DN) Note: JEDEC MO-229, variation WCED-3 proposal Table 29. TDFN8 – 8-lead thin dual flat, no-lead ( mm) ...
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STTS424E02 Figure 17. Carrier tape for DFN8 and TDFN8 packages T TOP COVER TAPE K 0 Table 30. Carrier tape dimensions for DFN8 and TDFN8 packages Package 8.00 1.50 1.75 +0.30 DFN8 +0.10/ ±0.10 –0.10 –0.00 8.00 ...
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Package mechanical data Figure 18. Reel schematic D A Full radius Table 31. Reel dimensions for 8 mm carrier tape - TDFN8 and DFN8 packages A B (max) (min) 180 mm 1.5 mm (7-inch) The dimensions given in parameters. 44/50 ...
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STTS424E02 10 Part numbering Table 32. Ordering information scheme Example: Device type (1) STTS424E02 Grade B: Maximum accuracy 75 ° °C = ± 1 °C C: Maximum accuracy 75 ° °C = ±2 °C Package DN ...
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Package marking information 11 Package marking information Figure 19. DA package topside marking information (DFN-8L) 1. Option codes accuracy grade. For example, E42C is C-grade. 2. Traceability codes Note: Contact local ST sales office for ...
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STTS424E02 12 Landing pattern The landing pattern recommendations per the JEDEC proposal for the TDFN package (DN) are shown in Figure The preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined for ...
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Landing pattern Table 33 lists variations of landing pattern implementations, ranked as “Preferred” and “Minimum Acceptable” based on the JEDEC proposal. Table 33. Parameters for landing pattern - TDFN package (DN) Parameter D2 Heat paddle width E2 Heat paddle height ...
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STTS424E02 13 Revision history Table 34. Document revision history Date Revision 13-Apr-2007 09-May-2007 04-Jun-2007 02-Jul-2007 18-Mar-2008 12-Jun-2008 08-Oct-2009 12-Oct-2010 1 Initial release. 2 Updated Table 27, 3 Updated Table 27. 4 Added POR threshold values to ...
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