ADM1021AARQ ON Semiconductor, ADM1021AARQ Datasheet - Page 11

• Manufacturer Part Number: ADM1021AARQ
• Description: IC SENSOR TEMP DUAL3/5.5V 16QSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1021AARQ

• Rohs Status: RoHS non-compliant
• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 100°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP

Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
2. Data is sent over the serial bus in sequences of
start condition, defined as a high−to−low transition
on the serial data line SDATA, while the serial
clock line SCLK remains high. This indicates that
an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition and shift in the next eight
bits, consisting of a 7−bit address (MSB first) plus
an R/W bit, which determines the direction of the
data transfer, that is, whether data will be written
to or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master writes
to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, because a low−to−high
transition when the clock is high can be interpreted
as a stop signal. The number of data bytes that can
be transmitted over the serial bus in a single read
or write operation is limited only by what the
master and slave devices can handle.
SDATA
SCLK
START BY
MASTER
A6
1
A5
SERIAL BUS ADDRESS BYTE
A4
A3
FRAME 1
A2
SDA (CONTINUED)
SCL (CONTINUED)
http://onsemi.com
A1
ADM1021A
A0
11
ADM1021A
R/W
ACK. BY
serial bus in one operation, but it is not possible to mix read
and write in one operation, because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
or two bytes, while read operations contain one byte.
data from it, the address pointer register must be set so that
the correct data register is addressed, data can then be written
into that register or read from it. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register.
over the bus followed by R/W set to 0. This is followed by
two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to
be written to the internal data register.
Any number of bytes of data can be transferred over the
For the ADM1021A, write operations contain either one
To write data to one of the device data registers or read
This is illustrated in Figure 14. The device address is sent
D7
1
9
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
D7
D 6
1
D5
D6
ADDRESS POINTER REGISTER BYTE
D5
D4
DATA BYTE
FRAME 3
D4
D3
FRAME 2
D3
D2
D2
D1
D1
D0
ADM1021A
ACK. BY
D0
9
ADM1021A
ACK. BY
STOP BY
9
MASTER