L6728ATR STMicroelectronics, L6728ATR Datasheet - Page 19

• Manufacturer Part Number: L6728ATR
• Description: IC CTLR PWM SGL HI FREQ 10VFQFPN
• Manufacturer: STMicroelectronics

Specifications of L6728ATR

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 67%
• Voltage - Supply: 5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-DFN
• Frequency-max: 660kHz
• Topology: Buck
• Output Voltage: 0.8 V
• Output Current: 1500 mA
• Switching Frequency: 660 KHz
• Duty Cycle (max): 67 %
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• For Use With: 497-8228 - BOARD EVALUATION W/L6728497-6418 - BOARD EVAL BASED ON L6728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8324-2

L6728A
10.2
10.3
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
Where ΔI
takes in consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitors supplies the current to the load or absorb the
current stored into the inductor until the converter reacts. In fact, even if the controller
recognizes immediately the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that also in this case
depends on the ESR and capacitive charge/discharge as follow:
Where ΔV
(
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation
during load transients while they does not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggested to minimize ripple as well as reducing voltage deviation in dynamic
mode.
Input capacitors
The input capacitor bank is designed considering mainly the input RMS current that
depends on the output deliverable current (I
follow:
The equation reaches its maximum value, I
input capacitor ESR and, in worst case, are:
D
MAX
⋅
V
IN
L
L
is the inductor current ripple. In particular, the expression that defines ΔV
–
is the voltage applied to the inductor during the transient response
V
OUT
for the load appliance or V
ΔV
ΔV
OUT_C
ΔV
OUT_C
I
ΔV
rms
P
OUT_ESR
OUT_ESR
=
=
=
=
ESR
I
ΔI
OUT
ΔI
OUT
OUT
OUT
L
=
⋅
OUT
⋅
=
⋅
(
ΔI
-------------------------------------- -
8 C
/2, with D = 0.5. The losses depends on the
I
) and the duty-cycle (D) for the regulation as
⋅
OUT
ΔI
D
------------------------------------- -
2 C
⋅
OUT
for the load removal).
L
⋅
⋅
L ΔI
(
OUT
⋅
1 D
2 ⁄
ESR
⋅
OUT
⋅
1
–
ESR
)
2
⋅
OUT
F
)
⋅
SW
ΔV
L
Application information
OUT_C
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