L6728DTR STMicroelectronics, L6728DTR Datasheet - Page 16

• Manufacturer Part Number: L6728DTR
• Description: IC PWM CTLR 1PH POWERGOOD 10DFN
• Manufacturer: STMicroelectronics

Specifications of L6728DTR

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 80%
• Voltage - Supply: 5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-DFN
• Frequency-max: 330kHz
• Duty Cycle (max): 80 %
• Mounting Style: SMD/SMT
• Switching Frequency: 300 KHz
• Operating Supply Voltage: 5 V to 12 V
• Supply Current: 6 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10432-2

Application details
10
10.1
16/33
Application details
Compensation network
The control loop shown in
regulated to the internal reference (when present, the offset resistor between the FB node
and GND can be neglected in control loop calculation).
The error amplifier output is compared to the oscillator sawtooth waveform to provide the
PWM signal to the driver section. The PWM signal is then transferred to the switching node
with V
The converter transfer function is the small signal transfer function between the output of the
EA and V
resonance and a zero at F
modulator is simply the input voltage V
ΔV
Figure 5.
The compensation network closes the loop, joining the V
function ideally equal to -Z
The compensation goal is to close the control loop while assuring high DC regulation
accuracy, good dynamic performance and stability. To achieve this, the overall loop needs
high DC gain, high bandwidth and good phase margin.
High DC gain is achieved by giving an integrator shape to the compensation network
transfer function. The loop bandwidth (F
ratio. However, for stability, it should not exceed F
the control loop gain must cross the 0 dB axis with -20 dB/decade slope.
As an example,
OSC
IN
.
amplitude. This waveform is filtered by the output filter.
OUT
PWM control loop
. This function has a double pole at frequency F
Figure 6
ΔV
OSC
shows an asymptotic bode plot of a type III compensation.
Figure 5
ESR
F
/Z
OSC
FB
Doc ID 16498 Rev 1
depending on the output capacitor ESR. The DC gain of the
COMPARATOR
.
AMPLIFIER
ERROR
C
F
_
+
is a voltage mode control loop. The output voltage is
PWM
C
P
IN
R
+
_
F
0dB
divided by the peak-to-peak oscillator voltage
V
) can be fixed by choosing the correct R
REF
Z
F
R
C
FB
S
SW
V
IN
R
/2π. To achieve a good phase margin,
S
Z
FB
L
OUT
R
C
LC
ESR
and EA output with transfer
OUT
depending on the L-C
V
OUT
F
L6728D
/R
OUT
FB