ISL6520BCBZ Intersil, ISL6520BCBZ Datasheet
ISL6520BCBZ
Specifications of ISL6520BCBZ
Related parts for ISL6520BCBZ
ISL6520BCBZ Summary of contents
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... PWM duty cycles range from 0% to 100%. Ordering Information TEMP. PART PART RANGE NUMBER MARKING (°C) PACKAGE ISL6520BCB* 6520 BCB SOIC ISL6520BCBZ* 6520 BCBZ SOIC (Note) (Pb-free) ISL6520BCR* 65 20BCR 4x4 QFN L16.4x4 ISL6520BCRZ* 65 20BCRZ 4x4 QFN (Note) (Pb-free) ISL6520BIR* 65 20BIR - 4x4 QFN L16 ...
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Pinouts ISL6520B (8 LD SOIC) TOP VIEW BOOT 1 UGATE 2 GND 3 LGATE 4 Block Diagram + 0. COMP/SD 20μA Typical Application 5V R PULLUP SHUTDOWN R OFFSET 2 ISL6520B 8 PHASE 7 COMP/ ...
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... Thermal Information Thermal Resistance SOIC Package (Note 7.0V (DC) QFN Package (Notes 2, 3 Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp SYMBOL TEST CONDITIONS I VCC POR f ISL6520BC, VCC = 5V OSC ISL6520BI, VCC = 5V Δ ...
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Functional Pin Description VCC This pin provides the bias supply for the ISL6520B, as well as the lower MOSFET’s gate. Connect a well-decoupled 5V supply to this pin. FB This pin is the inverting input of the internal error amplifier. ...
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ISL6520B. If there is nowhere for this current to go, such as to other distributed loads on the V rail, through a voltage limiting protection CC device, or other methods, the capacitance ...
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The modulator transfer function is the small-signal transfer function This function is dominated OUT E/A Gain and the output filter (L and break frequency at F and a zero at ...
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Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function ...
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ISL6520B may be circumvented by these MOSFETs if they have large parasitic impedences and/or capacitances that would inhibit the gate of the MOSFET from being discharged below it’s threshold level before the complementary MOSFET is ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...