L6728 STMicroelectronics, L6728 Datasheet - Page 15

• Manufacturer Part Number: L6728
• Description: IC PWM CTLR 1PH PWRGOOD 10-DFN
• Manufacturer: STMicroelectronics

Specifications of L6728

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 80%
• Voltage - Supply: 4.5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-DFN
• Frequency-max: 330kHz
• Output Voltage: 0.8 V
• Output Current: 30 A
• Input Voltage: 1.5 V to 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: 497-8228 - BOARD EVALUATION W/L6728497-6418 - BOARD EVAL BASED ON L6728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L6728
10
10.1
Application details
Compensation network
The control loop showed in
regulated to the internal reference (when present, offset resistor between FB node and GND
can be neglected in control loop calculation).
Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with V
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and V
resonance and a zero at F
modulator is simply the input voltage V
ΔV
Figure 5.
The compensation network closes the loop joining V
function ideally equal to -Z
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
stability, it should not exceed F
has to cross 0 dB axis with -20 dB/decade slope.
As an example,
OSC
.
OUT
PWM control loop
. This function has a double pole at frequency F
Figure 6
ΔV
OSC
shows an asymptotic bode plot of a type III compensation.
ESR
F
/Z
Figure 5
0dB
OSC
FB
SW
depending on the output capacitor ESR. The DC Gain of the
) can be fixed choosing the right R
COMPARATOR
.
AMPLIFIER
/2π. To achieve a good phase margin, the control loop gain
ERROR
C
F
_
+
PWM
C
is a voltage mode control loop. The output voltage is
P
IN
R
+
_
F
divided by the peak-to-peak oscillator voltage
V
REF
Z
F
R
C
FB
S
V
IN
R
OUT
S
Z
FB
L
and EA output with transfer
R
C
LC
ESR
OUT
depending on the L-C
F
/R
V
FB
OUT
Application details
ratio, however, for
IN
OUT
15/31