L6725A STMicroelectronics, L6725A Datasheet - Page 20

IC PWM CTLR VOLTAGE MODE SO-16N

L6725A

Manufacturer Part Number
L6725A
Description
IC PWM CTLR VOLTAGE MODE SO-16N
Manufacturer
STMicroelectronics
Datasheet

Specifications of L6725A

Pwm Type
Voltage Mode
Number Of Outputs
1
Frequency - Max
550kHz
Duty Cycle
100%
Voltage - Supply
4.5 V ~ 18 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
550kHz
Output Voltage
0.603 V
Input Voltage
1.8 V to 18 V
Switching Frequency
500 KHz
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Duty Cycle (max)
100 %
Package
SO16N
For Use With
497-5867 - EVAL BOARD 20A 250KHZ L6725497-5500 - EVAL BOARD FOR L6725
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
L6725A
Manufacturer:
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Quantity:
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Part Number:
L6725A
Manufacturer:
ST
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L6725ATR
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Application details
6.4
Figure 14. Compensation Network
20/32
Compensation network
The loop is based on a voltage mode control
internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output V
pulse-width modulated (PWM) with an amplitude of V
filtered by the output filter. The modulator transfer function is the small signal transfer function
of V
resonance and a zero at F
modulator is simply the input voltage V
The compensation network consists in the internal error amplifier, the impedance networks Z
(R3, R4 and C20) and Z
closed loop transfer function with the highest 0dB crossing frequency to have fastest transient
response (but always lower than f
load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade
slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation
networks, the following suggestions may be used:
OUT
/V
COMP
. This function has a double pole at frequency F
COMP
is then compared with the oscillator triangular waveform to provide a
FB
ESR
(R5, C18 and C19). The compensation network has to provide a
depending on the output capacitor’s ESR. The DC Gain of the
SW
/10) and the highest gain in DC conditions to minimize the
IN
divided by the peak-to-peak oscillator voltage: V
(Figure
14). The output voltage is regulated to the
IN
at the PHASE node. This waveform is
LC
depending on the L-C
L6725 - L6725A
OUT
OSC
IN
.

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