L6728D STMicroelectronics, L6728D Datasheet - Page 18

• Manufacturer Part Number: L6728D
• Description: IC CTLR PWM 1PH POWERGOOD 10DFN
• Manufacturer: STMicroelectronics

Specifications of L6728D

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 80%
• Voltage - Supply: 5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-DFN
• Frequency-max: 330kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application details
10.2
18/33
Layout guidelines
The L6728D provides control functions and high current integrated drivers to implement
high-current step-down DC-DC converters. In this type of application, a good layout is very
important.
The first priority when placing components for these applications must be reserved for the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure
copper traces. The loop must be minimized. The critical components, i.e. the power
MOSFETs, must be close to each other. The use of multi-layer printed circuit boards is
recommended.
The input capacitance (C
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred. MLCC are suggested to be
connected near the HS drain.
Use the appropriate number of VIAs when power traces have to move between different
planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover,
reproducing the same high-current trace on more than one PCB layer reduces the parasitic
resistance associated with that connection.
Connect output bulk capacitors (C
inductance and resistance associated with the copper trace, and also adding extra
decoupling capacitors along the way to the load when this results in being far from the bulk
capacitor bank.
b)
c)
d)
e)
f)
7) must be a part of a power plane and in any case constructed with wide and thick
Place F
Place F
Place F
Check that the compensation network gain is lower than open loop EA gain before
F
Check the phase margin obtained (it should be greater than 45°) and repeat if
necessary.
C
R
C
C
0dB
P
S
S
F
=
=
=
=
----------------------------------------------------------
2π R
-------------------------- -
----------------- - 1
2 F
------------------------------ -
π R
-----------------------------
π R
F
Z1
P1
Z2
⋅
⋅
⋅
SW
⋅
R
LC
S
below F
at F
at F
FB
F
1
1
F
⋅
⋅
–
F
⋅
F
C
SW
LC
ESR
LC
C
F
IN
F
⋅
and F
), or at least a portion of the total capacitance needed, must be
F
:
LC
ESR
Doc ID 16498 Rev 1
(typically 0.5*F
P2
–
OUT
1
at half of the switching frequency:
) as near as possible to the load, minimizing parasitic
LC
):
L6728D