L6728D STMicroelectronics, L6728D Datasheet - Page 21

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L6728D

Manufacturer Part Number
L6728D
Description
IC CTLR PWM 1PH POWERGOOD 10DFN
Manufacturer
STMicroelectronics
Datasheet

Specifications of L6728D

Pwm Type
Voltage Mode
Number Of Outputs
1
Frequency - Max
330kHz
Duty Cycle
80%
Voltage - Supply
5 V ~ 12 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 125°C
Package / Case
10-DFN
Frequency-max
330kHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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L6728D
11.2
11.3
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
Where ΔI
takes into consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitor supplies the current to the load or absorbs the
current stored into the inductor until the converter reacts. In fact, even if the controller
immediately recognizes the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that, in this case also,
depends on the ESR and capacitive charge/discharge as follows:
Where ΔV
(
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitances that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitances to minimize voltage deviation
during load transients, while they do not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggested to minimize ripple and reduce voltage deviation in dynamic mode.
Input capacitors
The input capacitor bank is designed considering mainly the input RMS current, which
depends on the output deliverable current (I
follows:
The equation reaches its maximum value, I
input capacitor’s ESR and, in the worst case, are:
ΔV
ΔV
ΔV
ΔV
I
P
rms
D
MAX
=
OUT_ESR
OUT_C
OUT_ESR
OUT_C
=
ESR
I
OUT
V
IN
L
=
=
L
(
is the inductor current ripple. In particular, the expression that defines ΔV
=
ΔI
=
ΔI
I
is the voltage applied to the inductor during the transient response
OUT
V
L
OUT
ΔI
ΔI
D
OUT
L
OUT
-------------------------------------- -
8 C
2 ⁄
(
1 D
ESR
)
------------------------------------- -
2 C
for the load appliance or V
2
OUT
ESR
L ΔI
1
)
OUT
F
OUT
SW
ΔV
Doc ID 16498 Rev 1
L
OUT
OUT
OUT
/2, with D = 0.5. The losses depend on the
) and the duty cycle (D) for regulation as
for the load removal).
Application information
OUT_C
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