ISL6569CRZ-T Intersil, ISL6569CRZ-T Datasheet

IC CTRLR PWM BUCK 2PHASE 32-QFN

ISL6569CRZ-T

Manufacturer Part Number
ISL6569CRZ-T
Description
IC CTRLR PWM BUCK 2PHASE 32-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6569CRZ-T

Pwm Type
Controller
Number Of Outputs
1
Frequency - Max
2MHz
Duty Cycle
75%
Voltage - Supply
4.75 V ~ 5.25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
Yes
Cuk
No
Isolated
No
Operating Temperature
0°C ~ 70°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Frequency-max
2MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Multi-Phase PWM Controller
The ISL6569 provides core-voltage regulation by driving two
interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6569 uses cost and space-saving r
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The reference and amplifiers are trimmed to ensure
a system accuracy of ±
Outstanding features of this controller IC include
Dynamic VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on V
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
TM
technology allowing seamless on-the-fly VID
1
% over temperature.
®
1
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
IN
, formed with an external
Data Sheet
DS(ON)
sensing
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Multi-Phase Power Conversion
• Active Channel Current Balancing
• Precision r
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
• Microprocessor Voltage Identification Input
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 2MHz)
• QFN Package:
• Pb-Free Available (RoHS Compliant)
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
December 29, 2004
- 2 Phase Operation
- Lossless
- Low Cost
- ±
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
- Near Chip Scale Package footprint, which improves
No Leads - Package Outline
PCB efficiency and has a thinner profile
1
% System Accuracy Over Temperature
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
DS(ON)
TM
Technology
Current Sharing
Dynamic VID™ is a trademark of Intersil Americas Inc.
ISL6569
FN9085.7

Related parts for ISL6569CRZ-T

ISL6569CRZ-T Summary of contents

Page 1

... A power good logic signal indicates when the converter output is between the UV and OV thresholds. 1 Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. December 29, 2004 Features • Multi-Phase Power Conversion - 2 Phase Operation • ...

Page 2

... Ld SOIC (See Note) (Pb-free) ISL6569CR 5x5 QFN L32.5x5 ISL6569CRZ 5x5 QFN (See Note) (Pb-free) *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 3

Block Diagram VID4 VID3 DYNAMIC VID2 VID DAC VID1 VID0 e/a FB COMP OFS x0.1 100µA VDIFF VSEN diff RGND AVERAGE IDROOP 3 ISL6569 PGOOD VCC EN 6V POR AND SOFT START ...

Page 4

Typical Application - 2 Phase Converter +12V 300Ω RGND VSEN VCC VDIFF PWM1 FB IOUT ISEN1 COMP ISL6569 OFS FS/DIS VID4 VID3 VID2 VID1 PWM2 VID0 PGOOD ISEN2 +12V EN GND 4 ISL6569 +12V PVCC BOOT UGATE VCC PHASE DRIVER ...

Page 5

Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V ...

Page 6

Electrical Specifications Operating Conditions: VCC = 5V, T PARAMETER ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth Slew Rate Maximum Output Voltage Source Current Sink Current REMOTE-SENSE AMPLIFIER Input Impedance Bandwidth Slew Rate SENSE CURRENT IOUT Accuracy ISEN Offset Voltage Over-Current Trip ...

Page 7

... Pull this pin below 1.14V, taking into account the enable hysteresis, to disable the controller once in operation. Connect a resistor divider to this pin to set the power-on voltage level for proper coordination with Intersil . If droop is DS(ON) MOSFET drivers. If this function is not required, simply tie this pin to VCC ...

Page 8

OFS x0.1 100µA COMP REFERENCE & DAC + + ERROR FB - AMPLIFIER IOUT I OUT - x 1 VDIFF + VSEN RGND FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF A ISL6569 CONVERTER Interleaving The switching of each channel in a ...

Page 9

V V – OUT OUT I = ----------------------------------------------------- - Equation 1, V and V are the input and output IN OUT voltages ...

Page 10

... Voltage Regulation The output of the error amplifier, V sawtooth waveform to modulate the pulse width of the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the , is ER specified reference voltage. Three distinct inputs to the error ...

Page 11

... The integrating compensation network shown in Figure 6 assures that the steady-state error in the output voltage is lim- ited to the error in the reference voltage (output of the DAC) plus offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed toler- TABLE 1. VOLTAGE IDENTIFICATION CODES VID3 VID2 ...

Page 12

ISL6569 to include all variations in current sources, amplifiers and the reference so that the output volt- age remains within the specified system tolerance of ± over temperature. LOAD-LINE REGULATION Microprocessor load current demands change from near ...

Page 13

... It is important that the driver ICs reach their POR level before the ISL6569 becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6569 with the HIP660X family of Intersil MOSFET drivers which require 12V bias. Third, the frequency select\disable input (FS/DIS) will shutdown the converter when pulled to ground ...

Page 14

Following the delay, the soft start ramps linearly until V reaches VID. For the system described above, this first linear ramp will continue for approximately – ---------- - RAMP1 DELAY 1.4 = 5.27ms The final ...

Page 15

... First, all PWM outputs are commanded low. Directing the Intersil drivers to turn on the lower MOSFETs; shunting the output to ground preventing any further increase in output voltage. The PWM outputs remain low until VDIFF falls to the programmed DAC level at which time they go into a high- impedance state ...

Page 16

MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET ...

Page 17

Balance). In this case, chose a new, smaller value of R for the affected phase. Choose R ISEN,2 desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. ∆ ...

Page 18

Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation the per-channel inductance, and C is the total output capacitance. Compensation The two ...

Page 19

The first step is to choose the desired bandwidth, f compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, f ...

Page 20

... Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil HIP660X drivers as close as possible to the MOSFETs they control to reduce the parasitics due to trace length between critical driver input and output signals ...

Page 21

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α µ 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in ...

Page 22

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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