ISL6308ACRZ-T Intersil, ISL6308ACRZ-T Datasheet

IC CTRLR PWM BUCK 3PHASE 40-QFN

ISL6308ACRZ-T

Manufacturer Part Number
ISL6308ACRZ-T
Description
IC CTRLR PWM BUCK 3PHASE 40-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6308ACRZ-T

Pwm Type
Voltage Mode
Number Of Outputs
1
Frequency - Max
275kHz
Duty Cycle
66.6%
Voltage - Supply
4.75 V ~ 5.25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
0°C ~ 70°C
Package / Case
40-VFQFN, 40-VFQFPN
Frequency-max
275kHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6308ACRZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Three-Phase Buck PWM Controller with
High Current Integrated MOSFET Drivers
The ISL6308A is a three-phase PWM control IC with
integrated MOSFET drivers. It provides a precision voltage
regulation system for multiple applications including, but not
limited to, high current low voltage point-of-load converters,
embedded applications and other general purpose low
voltage medium to high current applications.The integration
of power MOSFET drivers into the controller IC marks a
departure from the separate PWM controller and driver
configuration of previous multi-phase product families. By
reducing the number of external parts, this integration allows
for a cost and space saving power management solution.
Output voltage can be programmed using the on-chip DAC
or an external precision reference. A two bit code programs
the DAC reference to one of 4 possible values (0.6V,
0.9V,1.2V and 1.5V). A unity gain, differential amplifier is
provided for remote voltage sensing, compensating for any
potential difference between remote and local grounds. The
output voltage can also be offset through the use of single
external resistor. An optional droop function is also
implemented and can be disabled for applications having
less stringent output voltage variation requirements or
experiencing less severe step loads.
A unique feature of the ISL6308A is the combined use of
both DCR and r
positioning and overcurrent protection are accomplished
through continuous inductor DCR current sensing, while
r
balance. Using both methods of current sampling utilizes the
best advantages of each technique.
Protection features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the load. An OVP output is also provided to drive an optional
crowbar device. The overcurrent protection level is set
through a single external resistor. Other protection features
include protection against an open circuit on the remote
sensing inputs. Combined, these features provide advanced
protection for the output load.
Ordering Information
DS(ON)
ISL6308ACRZ* (Note)
ISL6308AIRZ* (Note)
ISL6308AEVAL1Z
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
current sensing is used for accurate channel-current
NUMBER
PART
DS(ON)
current sensing. Load line voltage
®
6308A CRZ
6308A IRZ
Evaluation Platform
1
MARKING
Data Sheet
PART
1-888-INTERSIL or 1-888-468-3774
TEMP. RANGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
-40 to +85
0 to +70
(°C)
Features
• Integrated Multi-Phase Power Conversion
• Precision Output Voltage Regulation
• Precision Channel Current Sharing
• Optional Load Line (Droop) Programming
• Variable Gate-Drive Bias - 5V to 12V
• Internal or External Reference Voltage Setting
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Operation Frequency up to 1.5MHz per Phase
• Digital Soft-Start
• Capable of Start-up in a Pre-Biased Load
• Pb-Free (RoHS Compliant)
Applications
• High Current DDR/Chipset Core Voltage Regulators
• High Current, Low Voltage DC/DC Converters
• High Current, Low Voltage FPGA/ASIC DC/DC Converters
- 1-, 2-, or 3-Phase Operation
- Differential Remote Voltage Sensing
- ±0.8% System Accuracy Over-Temperature
- ±0.5% System Accuracy Over-Temperature
- Usable for Output Voltages not Exceeding 2.3V
- Adjustable Reference-Voltage Offset
- Uses Loss-Less r
- Uses Loss-Less Inductor DCR Current Sampling
- On-Chip Adjustable Fixed DAC Reference Voltage with
- Reference can be Changed Dynamically
- Can use an External Voltage Reference
- OVP Pin to Drive Optional Crowbar Device
September 9, 2008
(for REF=0.6V and 0.9V)
(for REF=1.2V and 1.5V)
2-bit Logic Input Selects from Four Fixed Reference
Voltages (0.6V, 0.9V, 1.2V, 1.5V)
40 Ld 6x6 QFN (Pb-free)
40 Ld 6x6 QFN (Pb-free)
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
PACKAGE
Copyright Intersil Americas Inc. 2008. All Rights Reserved
DS(ON)
Current Sampling
ISL6308A
L40.6x6
L40.6x6
FN6669.0
DWG. #
PKG.

Related parts for ISL6308ACRZ-T

ISL6308ACRZ-T Summary of contents

Page 1

... Combined, these features provide advanced protection for the output load. Ordering Information PART PART NUMBER MARKING ISL6308ACRZ* (Note) 6308A CRZ ISL6308AIRZ* (Note) 6308A IRZ ISL6308AEVAL1Z Evaluation Platform *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. ...

Page 2

Pinout 3PH 2PH DAC REF OFST VCC COMP FB VDIFF RGND 2 ISL6308A ISL6308A (40 LD 6x6 QFN) TOP VIEW GND ...

Page 3

Block Diagram ICOMP DROOP ISEN AMP ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL6308A OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT ...

Page 4

Typical Application - ISL6308A FB VDIFF VSEN RGND 3PH +5V 2PH VCC OFST FS DAC ISL6308A REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ICOMP 4 ISL6308A +12V COMP PVCC1 BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V PVCC2 ...

Page 5

... VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL6308ACRZ 0°C to +70°C Ambient Temperature (ISL6308AIRZ .-40°C to +85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...

Page 6

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Maximum External Reference (Note 4) OFS ...

Page 7

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Lower Drive Sink Resistance OVER-TEMPERATURE SHUTDOWN ...

Page 8

Functional Pin Description VCC (Pin 6) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V supply and locally decouple using a quality 1.0µF ceramic capacitor. PVCC1, PVCC2, PVCC3 (Pins 33, 24, 18) Power supply pins for ...

Page 9

OFST (Pin 5) The OFST pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VDIFF. The offset current is generated via an external resistor and precision internal voltage references. ...

Page 10

7A/DIV 7A/DIV L3 PWM3, 5V/DIV PWM2, 5V/DIV I , 7A/DIV L1 PWM1, 5V/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER To understand the reduction of ripple current ...

Page 11

... Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current- balance method is illustrated in Figure 3, with error correction for channel 1 represented. In the figure, the cycle ...

Page 12

... DAC or the external voltage reference) and offset errors in the OFS current source, remote sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6308A to include the combined tolerances of each of these elements, except when an external reference or voltage divider is used, then the tolerances of these components has to be taken into account ...

Page 13

EXTERNAL CIRCUIT ISL6308A INTERNAL CIRCUIT COMP VID DAC DAC REF C REF OFS I OFS - VDIFF VSEN OUT - RGND DROOP - V DROOP ...

Page 14

By simply adjusting the value the load line can be set to S any level, giving the converter the right amount of droop at all load currents. It may also be necessary to compensate for any changes ...

Page 15

PHASE node. This reduces voltage stress on the boot to phase pins. The bootstrap capacitor must have a maximum voltage rating above PVCC + 5V and its capacitance value can be chosen from Equation 11: Q ...

Page 16

The Output soft-start time begins with a delay SS period equal to 64 switching cycles after the ENLL has exceeded its POR level, followed by a ...

Page 17

The ISL6308A constantly monitors the difference between the VSEN and RGND voltages to detect if an overvoltage event occurs. Before, and during soft-start, while the DAC/REF is ramping up, the overvoltage trip level is V successful soft-start, the overvoltage trip ...

Page 18

... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. ...

Page 19

At turn on, the upper MOSFET begins to conduct and this transition occurs over a time Equation 17, the 2 approximate power loss UP,2 ⎛ ⎞ ⎛ ⎞ ≈ ...

Page 20

The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive ...

Page 21

Figure 18. Follow the steps below to ensure the R-C and inductor L/DCR time constants are matched accurately. 1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, ...

Page 22

Case 3: F > -------------------------------- - ⋅ ⋅ 0 2π C ESR ⋅ ⋅ 2π OSC ⋅ ----------------------------------------------- ⋅ ⋅ 0. ⋅ ⋅ 0.66 V ESR ...

Page 23

Phase margin is the difference between the closed loop phase at F 0dB equations that follow relate the compensation network’s poles, zeros and gain to the components ( Figure 20 ...

Page 24

⎛ ⎞ log ------- - ⎝ ⎠ LOG FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN respond. Because it has a ...

Page 25

SWITCHING FREQUENCY (Hz) FIGURE 23 SWITCHING FREQUENCY FS Input Capacitor Selection The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. ...

Page 26

PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current ...

Page 27

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 28

Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ...

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