ISL6308IRZ-T Intersil, ISL6308IRZ-T Datasheet
ISL6308IRZ-T
Specifications of ISL6308IRZ-T
Related parts for ISL6308IRZ-T
ISL6308IRZ-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6308 FN9208 ...
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... ISL6308CRZ ISL6308 CRZ ISL6308CRZ-T* ISL6308 CRZ ISL6308IRZ ISL6308 IRZ ISL6308IRZ-T* ISL6308 IRZ ISL6308EVAL1Z Evaluation Platform * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). ...
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Block Diagram ICOMP DROOP ISEN AMP ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL6308 OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT ...
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Typical Application - ISL6308 FB VDIFF VSEN RGND 3PH +5V 2PH VCC OFST FS DAC ISL6308 REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ICOMP 4 ISL6308 +12V COMP PVCC1 BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V PVCC2 ...
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... BOOT + 0.3V BOOT Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL6308CRZ 0°C to +70°C Ambient Temperature (ISL6308IRZ .-40°C to +85°C TEST CONDITIONS I ; ENLL = high VCC I ; ENLL = high; all gate outputs open, F PVCC ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER ERROR AMPLIFIER DC Gain (Note 3) ...
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Timing Diagram t PDHUGATE UGATE LGATE t FLGATE Simplified Power System Diagram +12V IN + REF0,REF1 ENLL OVP PGOOD Functional Pin Description VCC (Pin 6) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V ...
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REF0 and REF1 (Pins 40, 39) These pins make up the 2-bit input that selects the fixed DAC reference voltage. These pins respond to TTL logic thresholds. The ISL6308 decodes these inputs to establish one of four fixed reference voltages; ...
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PHASE1, PHASE2, and PHASE3 (Pins 29, 28, 22) Connect these pins to the sources of the upper MOSFETs. These pins are the return path for the upper MOSFETs’ drives. LGATE1, LGATE2, and LGATE3 (Pins 34, 23, 17) These pins are ...
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... Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current-balance method is illustrated in Figure 3, with error correction for Channel 1 represented. In Figure 3, the cycle average ...
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V COMP + - - SAWTOOTH SIGNAL FILTER f( AVG ÷ NOTE: CHANNEL 2 AND 3 ARE OPTIONAL. FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT- BALANCE ADJUSTMENT Current Sampling In ...
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... DAC or the external voltage reference) and offset errors in the OFS current source, remote sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6308 to include the combined tolerances of each of these elements, except when an external reference or voltage divider is used, then the tolerances of these components has to be taken into account ...
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Load Line (Droop) Regulation In some high current applications, a requirement on a precisely controlled output impedance is imposed. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. The Droop is an optional ...
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VDIFF + V R OFS 1 VREF - FB I OFS OFS ISL6308 R OFS GND FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING VDIFF - V R OFS 1 VREF + FB I OFS VCC R OFS OFS ISL6308 FIGURE ...
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Q = 100nC GATE 0.4 50nC 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 ΔV BOOT_CAP FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE Gate Drive Voltage Versatility The ISL6308 provides the user ...
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DAC 1280 + ------------------------------------------- - For example, a regulator with 450kHz switching frequency having REF voltage set ...
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Overvoltage Protection The ISL6308 constantly monitors the difference between the VSEN and RGND voltages to detect if an overvoltage event occurs. Before, and during soft-start, while the DAC/REF is ramping up, the overvoltage trip level is V successful soft-start, the ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. ...
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MOSFET across V dissipated as a result UP,3 ⋅ ⋅ Finally, the resistive part of the upper MOSFET is given in Equation 19 ...
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P DR estimated as DR_UP DR_LOW BOOT P Qg_Q1 P --------------------- = BOOT 3 ⎛ HI1 LO1 ⎜ P -------------------------------------- --------------------------------------- - = + ...
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Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, with L = 1µH and DCR = 1mΩ, set the oscilloscope to 500µs/div. 2. Record ΔV1 and ΔV2 as shown in Figure 18. 3. Select ...
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Case 3: F > -------------------------------- - ⋅ ⋅ 0 2π C ESR ⋅ ⋅ 2π OSC ⋅ ----------------------------------------------- ⋅ ⋅ 0. ⋅ ⋅ 0.66 V ESR ...
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F 0dB equations that follow relate the compensation network’s poles, zeros and gain to the components ( Figure 20 and 21. Use the following guidelines for 3 locating ...
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⎛ R2 ⎞ 20 log ------- - ⎝ ⎠ LOG FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN Output Filter Design The output ...
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Switching frequency is determined by the selection of the frequency-setting resistor Figure 23 and Equation 43 FS are provided to assist in selecting the correct value for ⋅ 10.61 1.035 – log F ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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COMP VDIFF VSEN RGND 3PH +5V 2PH VCC C HF0 R OFST OFST DAC ISL6308 R REF REF C REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF ...
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Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ...