ISL6569ACR Intersil, ISL6569ACR Datasheet

IC CTRLR PWM BUCK 2PHASE 32-QFN

ISL6569ACR

Manufacturer Part Number
ISL6569ACR
Description
IC CTRLR PWM BUCK 2PHASE 32-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6569ACR

Pwm Type
Voltage/Current Mode
Number Of Outputs
1
Frequency - Max
2MHz
Duty Cycle
75%
Voltage - Supply
4.75 V ~ 5.25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
0°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Frequency-max
2MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6569ACR
Manufacturer:
INTERSIL
Quantity:
200
Part Number:
ISL6569ACR
Manufacturer:
INTERSIL
Quantity:
818
Part Number:
ISL6569ACR
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INTERSIL
Quantity:
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Multi-Phase PWM Controller
The ISL6569A provides core-voltage regulation by driving
two interleaved synchronous-rectified buck-converter
channels in parallel. Interleaving the channel timing results
in increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6569A uses cost and space-saving r
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The reference and amplifiers are trimmed to ensure
a system accuracy of ±0.5% over temperature.
Outstanding features of this controller IC include
Dynamic VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on V
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
TM
technology allowing seamless on-the-fly VID
®
1
IN
, formed with an external
Data Sheet
DS(ON)
sensing
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Multi-Phase Power Conversion
• Active Channel Current Balancing
• Precision r
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
• Microprocessor Voltage Identification Input
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 2MHz)
• QFN Package:
• Pb-Free Available (RoHS Compliant)
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
Ordering Information
ISL6569ACB
ISL6569ACBZ (Note) 0 to 70 24 Ld SOIC (Pb-free)
ISL6569ACR
ISL6569ACRZ (Note) 0 to 85 32 Ld 5x5 QFN (Pb-free) L32.5x5
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
December 29, 2004
- 2 Phase Operation
- Lossless
- Low Cost
- ±
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID
- Compliant to JEDEC PUB95 MO-220
- Near Chip Scale Package footprint, which improves
PART NUMBER
QFN - Quad Flat No Leads - Package Outline
PCB efficiency and has a thinner profile
0.5
All other trademarks mentioned are the property of their respective owners.
% System Accuracy Over Temperature
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
DS(ON)
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
TM
Technology
Current Sharing
TEMP.
0 to 70 24 Ld SOIC
0 to 85 32 Ld 5x5 QFN
(
o
C)
PACKAGE
ISL6569A
FN9092.2
M24.3
M24.3
L32.5x5
DWG. #
PKG.

Related parts for ISL6569ACR

ISL6569ACR Summary of contents

Page 1

... ISL6569ACB ISL6569ACBZ (Note SOIC (Pb-free) ISL6569ACR ISL6569ACRZ (Note 5x5 QFN (Pb-free) L32.5x5 Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 2

... VID3 VID2 5 VID1 VID0 18 OFS 8 17 COMP IOUT 12 13 VDIFF 2 ISL6569A EN FS/DIS PGOOD ISEN1 PWM1 VID2 PWM2 VID1 GND ISEN2 VID0 VCC GND RGND OFS VSEN COMP ISL6569ACR (32 LD 5x5 QFN) TOP VIEW ISEN1 21 PWM1 20 PWM2 19 GND 18 ISEN2 FN9092.2 December 29, 2004 ...

Page 3

Block Diagram VID4 VID3 DYNAMIC VID2 VID DAC VID1 VID0 e/a FB COMP OFS x0.1 100µA VDIFF 2.2V VSEN diff RGND AVERAGE IDROOP 3 ISL6569A PGOOD VCC EN 6V POR AND SOFT START ...

Page 4

Typical Application - 2 Phase Converter +12V VSEN RGND VCC VDIFF PWM1 FB IOUT ISEN1 COMP ISL6569A OFS FS/DIS VID4 VID3 VID2 VID1 PWM2 VID0 PGOOD ISEN2 +12V EN GND 4 ISL6569A +12V 300Ω PVCC BOOT UGATE VCC PHASE DRIVER ...

Page 5

Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V ...

Page 6

Electrical Specifications Operating Conditions: VCC = 5V, T PARAMETER Disable Voltage Sawtooth Amplitude Max Duty Cycle ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth Slew Rate Maximum Output Voltage Source Current Sink Current REMOTE-SENSE AMPLIFIER Input Impedance Bandwidth Slew Rate SENSE CURRENT ...

Page 7

... ISL6569A VCC Supplies all the power necessary to operate the chip. The IC ISL6569ACR starts to operate when the voltage on this pin exceeds the 32 LEAD QFN 5x5 rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply or through a series 255Ω ...

Page 8

OFS x0.1 100µA COMP REFERENCE & DAC + + ERROR FB - AMPLIFIER IOUT I OUT - VDIFF VSEN RGND FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF A ISL6569A CONVERTER Interleaving The switching of each channel in a ...

Page 9

In addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases. To understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel’s peak-to-peak inductor ...

Page 10

... V signal is compared to a sawtooth ramp signal and produces a pulse width which corrects for any unbalance and drives the error current toward zero. Figure 6 illustrates Intersil’s patented current balance method as implemented on one channel of a multi-phase converter. Two considerations designers face are MOSFET selection and inductor design ...

Page 11

... The output of the error amplifier, V COMP sawtooth waveform to modulate the pulse width of the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. Three distinct inputs to the error amplifier determine the voltage level of V and external circuitry which control voltage regulation is illustrated in Figure 6 ...

Page 12

TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 LOAD-LINE REGULATION Microprocessor load current demands ...

Page 13

... It is important that the driver ICs reach their POR level before the ISL6569A becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6569A with the HIP660X family of Intersil MOSFET drivers which require 12V bias. Third, the frequency select/disable input (FS/DIS) will shutdown the converter when pulled to ground ...

Page 14

... ISL6569A to protect the microprocessor load. First, all PWM outputs are commanded low. Directing the Intersil drivers to turn on the lower MOSFETs; shunting the output to ground preventing any further increase in output voltage. The PWM outputs remain low until VDIFF falls to the ...

Page 15

... The Intersil drivers respond by turning off both upper and lower MOSFETs. If the over-voltage condition reoccurs, the ISL6569A will again command the lower MOSFETs to turn on. The ISL6569A will continue to protect the load in this fashion as long as the over-voltage repeats. Second, the OVP pin pulls to VCC and can deliver 100mA ...

Page 16

Equation 1 the duty cycle ( the per-channel inductance   –  M  -------------------------------- ...

Page 17

Load-Line Regulation Resistor The load-line regulation resistor is labeled R Its value depends on the desired full-load droop voltage (V in Figure 6). If Equation 19 is used to select each DROOP ISEN resistor, the load-line regulation resistor is as ...

Page 18

COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The ...

Page 19

COMP IOUT VDIFF FIGURE 14. COMPENSATION CIRCUIT FOR ISL6569A BASED CONVERTER WITHOUT LOAD-LINE REGULATION In the solutions to the compensation equations, there is a single degree of ...

Page 20

... Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil HIP660X drivers as close as possible to the MOSFETs they control to reduce the parasitics due to trace length between critical driver input and output signals ...

Page 21

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α µ 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in ...

Page 22

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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