MC44608P100 ON Semiconductor, MC44608P100 Datasheet - Page 8

• Manufacturer Part Number: MC44608P100
• Description: IC PWM FLYBCK ISO VM 8DIP
• Manufacturer: ON Semiconductor

Specifications of MC44608P100

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 110kHz
• Duty Cycle: 86%
• Voltage - Supply: 6.6 V ~ 13 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Frequency-max: 110kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC44608P100OS

follows (refer to Figure 7):
the regulation block reacts by increasing the ON time (dmax
= 80%). The OC is reached at the end of every switching
cycle. The LW latch (Figure 8) is reset before the VPWM
signal appears. The SMPS output voltage is low. The V
voltage cannot be maintained at a normal level as the
auxiliary winding provides a voltage which is also reduced
in a ratio similar to the one on the output (i.e. Vout nominal
/ Vout short−circuit). Consequently the V
reduced at an operating rate given by the combination V
capacitor value together with the I
(3.2 mA) according to the equation 2. When V
10V the WORKING PHASE gets terminated. The LW latch
remains in the reset status.
voltage continues to drop. When it reaches 6.5 V this phase
is terminated. Its duration is governed by equation 3.
start−up current source (−I
MODE latch is reset. The V
to the equation 1. When it reaches 13 V, the IC enters into the
SWITCHING PHASE.
current source is inhibited, the MODE latch (Q=0) activates
the NORMAL mode of operation. Figure 3 shows that no
current is injected out pin 2. The over current sense level
corresponds to 1.0 V.
The SWITCHING PHASE duty cycle is in the range of 10%.
to the typical application schematic on page 13). The high
voltage output value becomes lower than the NORMAL
mode regulated value. The TL431 shunt regulator is fully
OFF. In the SMPS stand−by mode all the SMPS outputs are
lowered except for the low voltage output that supply the
wake−up circuit located at the isolated side of the power
supply. In that mode the secondary regulation is performed
by the zener diode connected in parallel to the TL431.
the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the
Demagnetization Section). In the reconfigured status, the
Laux voltage is also reduced. The V
longer possible thus the SMPS enters in a hiccup mode
similar to the one described under the Overload condition.
mode. The current sense clamping level is reduced
2. Overload
In the hiccup mode the 3 distinct phases are described as
The SWITCHING PHASE: The SMPS output is low and
The LATCHED−OFF PHASE: The V
The START−UP PHASE is reinitiated. The high voltage
The NEXT SWITCHING PHASE: The high voltage
As long as the overload is present, this sequence repeats.
3. Transition from Normal to Pulsed Mode
In this sequence the secondary side is reconfigured (refer
The secondary reconfiguration status can be detected on
In the SMPS stand−by mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload
CC1
CC
= 9.0 mA) is activated and the
voltage ramps up according
CC
CC
working consumption
self−powering is no
CC
CC
CC
voltage is
capacitor
crosses
http://onsemi.com
CC
CC
MC44608
8
according to the equation of the current sense section,
page 5. The C.S. clamping level depends on the power to be
delivered to the load during the SMPS stand−by mode.
Every switching sequence ON/OFF is terminated by an OC
as long as the secondary Zener diode voltage has not been
reached. When the Zener voltage is reached the ON cycle is
terminated by a true PWM action. The proper SWITCHING
PHASE termination must correspond to a NOC condition.
The LW latch stores this NOC status.
The MODE latch remains in its set status (Q=1).
validated and the 200 mA is sourced out of the Current Sense
pin 2.
regulation on the low voltage secondary rail can no longer
be achieved, thus at the end of the SWITCHING PHASE, no
PWM condition can be encountered. The LW latch is reset.
takes place.
constant on the secondary side of the SMPS an additional
reset input R2 is provided on the MODE latch. The condition
Idemag<24 mA corresponds to the activation of the
secondary reconfiguration status. The R2 reset insures a
direct return into the Normal Mode.
Pulsed Mode Duty Cycle Control
closed and the control input pin 3 is connected to a 4.6 V
voltage source thru a 500 W resistor. The discharge rate of
the V
during the LATCHED OFF phase) in addition to the current
drawn out of the pin 3. Connecting a resistor between the
Pin 3 and GND (R
drawn from the V
LATCHED OFF phase is impacted by the presence of the
resistor R
pin 3 current.
Pulsed Mode Phases
behavior during the PULSED MODE operation. The
equations 6, 7, and 8 contain K, Y, and D factors. These
factors are combinations of measured parameters. They
appear in the parameter section “Kfactors for pulsed mode
operation” page 4. In equations 3 through 8 the pin 3 current
is the current defined in the above section “Pulsed Mode
Duty Cycle Control”.
The LATCHED OFF PHASE: The MODE latch is set.
The START−UP PHASE is similar to the Overload Mode.
The SWITCHING PHASE: The Stand−by signal is
4. Transition from Stand−by to Normal
The secondary reconfiguration is removed. The
At the next WORKING PHASE a NORMAL mode status
In order to become independent of the recovery time
During the sleep mode of the SMPS the switch S3 is
Equations 1 through 8 define and predict the effective
CC
capacitor is given by I
DPULSED
. The equation 3 shows the relation to the
CC
DPULSED
through pin 3. The duration of the
) a programmable current is
CC−latch
(device consumption