ISL6334CCRZ Intersil, ISL6334CCRZ Datasheet

IC CTRLR PWM SYNC BUCK 40-QFN

ISL6334CCRZ

Manufacturer Part Number
ISL6334CCRZ
Description
IC CTRLR PWM SYNC BUCK 40-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6334CCRZ

Applications
Controller, Intel VR11.1
Voltage - Input
3 ~ 12 V
Number Of Outputs
1
Voltage - Output
0.5 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN, 40-VFQFPN
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
VR11.1, 4-Phase PWM Controller with
Light Load Efficiency Enhancement and
Load Current Monitoring Features
The ISL6334B, ISL6334C control microprocessor core
voltage regulation by driving up to 4 interleaved
synchronous-rectified buck channels in parallel. This
multiphase architecture results in multiplying channel ripple
frequency and reducing input and output ripple currents.
Lower ripple results in fewer components, lower cost, reduced
power dissipation, and smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates and require high efficiency at light
load. The ISL6334B, ISL6334C utilizes Intersil’s proprietary
Active Pulse Positioning (APP), Adaptive Phase Alignment
(APA) modulation scheme, active phase adding and
dropping to achieve and maintain the extremely fast
transient response with fewer output capacitors and high
efficiency from light to full load.
The ISL6334B, ISL6334C is designed to be compliant to
Intel VR11.1 specifications. It accurately reports the load
current via IMON pin to the microprocessor, which sends an
active low PSI# signal to the controller at low power mode.
The controller then enters 1- or 2-phase operation with diode
emulation option to reduce magnetic core and switching
losses, yielding high efficiency at light load. After the PSI#
signal is de-asserted, the dropped phase(s) are added back
to sustain heavy load transient response and efficiency.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6334B,
ISL6334C senses the output current continuously by utilizing
patented techniques to measure the voltage across the
dedicated current sense resistor or the DCR of the output
inductor. The sensed current flows out of FB pin to develop the
precision voltage drop across the feedback resistor for droop
control. Current sensing circuits also provide the needed
signals for channel-current balancing, average overcurrent
protection and individual phase current limiting. A NTC
thermistor’s temperature is sensed via TM pin and internally
digitized for thermal monitoring and for integrated thermal
compensation of the current sense elements.
A unity gain, differential amplifier is provided for remote voltage
sensing and completely eliminates any potential difference
between remote and local grounds. This improves regulation
and protection accuracy. The threshold-sensitive enable input is
available to accurately coordinate the start-up of the ISL6334B,
ISL6334C with any other voltage rail. Dynamic-VID™
technology allows seamless on-the-fly VID changes. The
offset pin allows accurate voltage offset settings that are
independent of VID setting.
®
1
Data Sheet
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Intel VR11.1 Compliant
• H_CPURST_N Input to Eliminate Required Extensive
• Proprietary Active Pulse Positioning (APP) and Adaptive
• Proprietary Active Phase Adding and Dropping with Diode
• Precision Multiphase Core Voltage Regulation
• Precision Resistor or DCR Differential Current Sensing
• Microprocessor Voltage Identification Input
• Average Overcurrent Protection and Channel Current Limit
• Precision Overcurrent Protection on IMON Pin
• Thermal Monitoring and Overvoltage Protection
• Integrated Programmable Temperature Compensation
• Integrated Open Sense Line Protection
• 1 to 4-Phase Operation, Coupled Inductor Compatibility
• Adjustable Switching Frequency up to 1MHz Per Phase
• Package Option
• Pb-Free (RoHS Compliant)
External Circuitry for Proper PSI# Operation of Intel’s
Eaglelake Chipset Platforms
Phase Alignment (APA) Modulation Scheme
Emulation Scheme For Enhanced Light Load Efficiency
- Differential Remote Voltage Sensing
- ±0.5% Closed-loop System Accuracy Over Load, Line
- Bi-directional, Adjustable Reference-Voltage Offset
- Accurate Load-Line (Droop) Programming
- Accurate Channel-Current Balancing
- Accurate Load Current Monitoring via IMON Pin
- Dynamic VID™ Technology for VR11.1 Requirement
- 8-Bit VID, VR11 Compatible
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
and Temperature
Flat No Leads - Product Outline
August 31, 2010
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008-2010. All Rights Reserved
ISL6334B, ISL6334C
FN6689.2

Related parts for ISL6334CCRZ

ISL6334CCRZ Summary of contents

Page 1

... Pb-Free (RoHS Compliant) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008-2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. FN6689.2 ...

Page 2

... IRZ ISL6334CIRZ 6334C IRZ ISL6334BCRZ 6334B CRZ ISL6334CCRZ 6334C CRZ NOTES: 1. Add “-T” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

Page 3

... ISL6596, ISL6609 5V ISL6614, ISL6614A 12V ISL6610, ISL6610A 5V NOTE: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow for dual footprint layout implementation to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous Channels. 3 ISL6334B, ISL6334C COMMENTS # OF DIODE ...

Page 4

ISL6334B and ISL6334C Block Diagram VDIFF - RGND X1 + VSEN SOFT-START + OVP - FAULT LOGIC +175mV SS VID7 VID6 VID5 DYNAMIC VID4 VID VID3 D/A VID2 VID1 VID0 DAC OFFSET OFS REF FB COMP 1.11V + OCP - ...

Page 5

Typical Application: 4-Phase VR with Thermal Compensation, 1-Phase PSI#, DE, and GVOT COMP VCC FB VDIFF VSEN RGND EN_VTT VTT VR_RDY VID7 ISL6334 ISL6334B VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# H_CPURST_N VR_HOT VIN EN_PWR +5V GND IMON TCOMP ...

Page 6

Typical Application - 4-Phase VR with 1-Phase PSI#; without DE and GVOT COMP VCC FB VDIFF VSEN RGND EN_VTT VTT VR_RDY VID7 ISL6334 ISL6334C VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# H_CPURST_N VR_HOT VIN EN_PWR +5V GND IMON TCOMP ...

Page 7

Typical Application - CI VR with External Thermal Compensation, 2-Phase PSI# (no DE and GVOT) NTC COMP VCC VDIFF VSEN RGND EN_VTT VTT VR_RDY VID7 VID6 ISL6334 VID5 ISL6334C VID4 VID3 VID2 VID1 VID0 PSI# VR_FAN H_CPURST_N ...

Page 8

... Recommended Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature ISL6334BCRZ, ISL6334CCRZ 0°C to +70°C ISL6334BIRZ, ISL6334CIRZ . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty ...

Page 9

Electrical Specifications Recommended Operating Conditions; VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS Pin OSCILLATORS Accuracy of Switching Frequency Setting ...

Page 10

Electrical Specifications Recommended Operating Conditions; VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued) PARAMETER Peak Current Limit for Individual Channel IMON Clamped and OCP Trip Level ...

Page 11

... VCC. See “PWM and PSI# Operation” on page 13 for details. PWM1-4 - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM2, PWM3 and PWM4. Tie PWM2 to VCC to configure for 1-phase operation ...

Page 12

ISEN1-4+, ISEN1-4- - The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs left ...

Page 13

... Figure 21 shows the single phase input-capacitor RMS current for comparison. PWM Modulation Scheme The ISL6334B, ISL6334C adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads ...

Page 14

... The matching driver's internal PWM resistor divider can further raise the PWM potential, but not lower it below the level set by the controller IC. Therefore, the controller's PWM outputs are directly compatible with Intersil drivers that require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM signal amplitudes are generally incompatible. ...

Page 15

INDUCTOR DCR SENSING An inductor’s winding is characteristic of a distributed resistance, as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 4. The channel current I , ...

Page 16

... Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil’s patented current-balance method. Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area ...

Page 17

TABLE 2. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...

Page 18

TABLE 2. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...

Page 19

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results ...

Page 20

... POR level before the ISL6334B, ISL6334C becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6334B, ISL6334C with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR ...

Page 21

... At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns). This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC plus 75mV, PWM signals enter a high-impedance state ...

Page 22

... SW At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns, commanding the Intersil MOSFET driver ICs to turn off 22 ISL6334B, ISL6334C both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft-start ...

Page 23

TEMPERATURE (°C) FIGURE 13. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE WITH RECOMMENDED PARTS We recommend using those resistors for the accurate temperature compensation. There ...

Page 24

... It is assumed that the reader is familiar with . TC2 many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete (EQ. 22) reference designs, which include schematics, bills of materials, and example board layouts for all common microprocessor applications. ...

Page 25

Power Stages The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily upon the cost analysis, which in turn depends on system constraints that differ from one design to the next. ...

Page 26

With integrated temperature compensation, the sensed current signal is independent on the operational temperature of the power stage, i.e. the temperature effect on the current sense element R is ...

Page 27

The feedback resistor has already been chosen as FB outlined in “Load-Line Regulation Resistor” on page 26. Select a target bandwidth for the compensated system, f The target bandwidth must be large enough to assure adequate transient performance, ...

Page 28

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output ...

Page 29

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 30

Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 30 ...

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