IC CONTROLLER INTEL 24SOIC

ISL6530CB-T

Manufacturer Part NumberISL6530CB-T
DescriptionIC CONTROLLER INTEL 24SOIC
ManufacturerIntersil
Series-
ISL6530CB-T datasheet
 


Specifications of ISL6530CB-T

ApplicationsController, Intel Pentium® III, IVVoltage - Input4.5 ~ 5.5 V
Number Of Outputs2Voltage - Output2.5V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case24-SOIC (7.5mm Width)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other namesISL6530CB-TR  
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Data Sheet
Dual 5V Synchronous Buck Pulse-Width
Modulator (PWM) Controller for DDRAM
Memory V
and V
Termination
DDQ
TT
The ISL6530 provides complete control and protection for
dual DC-DC converters optimized for high-performance
DDRAM memory applications. It is designed to drive low
cost N-channel MOSFETs in synchronous-rectified buck
topology to efficiently generate 2.5V V
DDQ
DDRAM memory, V
for DDRAM differential signalling,
REF
and V
for signal termination. The ISL6530 integrates all of
TT
the control, output adjustment, monitoring and protection
functions into a single package.
The V
output of the converter is maintained at 2.5V
DDQ
through an integrated precision voltage reference. The V
output is precisely regulated to 1/2 the memory power
supply, with a maximum tolerance of ±1% over temperature
and line voltage variations. V
accurately tracks V
TT
During V2_SD sleep mode, the V
output is maintained by
TT
a low power window regulator.
The ISL6530 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes two
phase-locked 300kHz triangle-wave oscillators which are
o
displaced 90
to minimize interference between the two
PWM regulators. The regulators feature error amplifiers with
a 15MHz gain-bandwidth product and 6V/µs slew rate which
enables high converter bandwidth for fast transient
performance. The resulting PWM duty ratio ranges from 0%
to 100%.
The ISL6530 protects against over-current conditions by
inhibiting PWM operation. The ISL6530 monitors the current
in the V
regulator by using the r
DDQ
DS(ON)
MOSFET which eliminates the need for a current sensing
resistor.
Ordering Information
TEMP
o
PART NUMBER
RANGE(
C)
PACKAGE
ISL6530CB*
0 to 70
24 Lead SOIC
ISL6530CBZ*
0 to 70
24 Lead SOIC
(See Note)
(Pb-free)
ISL6530CR*
0 to 70
32 Lead 5x5 QFN
ISL6530CRZ*
0 to 70
32 Lead 5x5 QFN
(See Note)
(Pb-free)
ISL6530EVAL1, 2
Evaluation Board
* Add “-T” suffix for tape and reel option.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
November 15, 2004
Features
• Provides V
channel DDRAM memory systems
• Excellent voltage regulation
= 2.5V ±2% over full operating range
- V
DDQ
- V
= (V
REF
- V
= V
TT
for powering
• Supports ‘S3’ sleep mode
- V
is held at V
TT
to minimize wake-up time
• Fast transient response
- Full 0% to 100% duty ratio
REF
• Operates from +5V input
• Overcurrent fault monitor on VDD
- Does not require extra current sensing element
.
REF
- Uses MOSFET’s r
• Drives inexpensive N-Channel MOSFETs
• Small converter size
- 300kHz fixed frequency oscillator
• 24 Lead, SOIC or 32 Lead, 5mm×5mm QFN
• Pb-Free Available (RoHS Compliant)
Applications
• V
, V
DDQ
TT
systems
- Main Memory in AMD® Athlon™ and K8™, Pentium®
III, Pentium IV, Transmeta, PowerPC™, AlphaPC™, and
UltraSparc® based computer systems
of the upper
- Video memory in graphics systems
• High-power tracking DC-DC regulators
PKG.
DWG. #
M24.3
M24.3
L32.5x5
L32.5x5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
1-888-INTERSIL or 321-724-7143
Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6530
FN9052.2
, V
, and V
voltages for one- and two-
DDQ
REF
TT
÷2) ±1% over full operating range
DDQ
± 30mV
REF
÷2 via low power window regulator
DDQ
DS(ON)
, and VREF regulation for DDRAM memory
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved.

ISL6530CB-T Summary of contents

  • Page 1

    ... DDQ DS(ON) MOSFET which eliminates the need for a current sensing resistor. Ordering Information TEMP o PART NUMBER RANGE( C) PACKAGE ISL6530CB Lead SOIC ISL6530CBZ Lead SOIC (See Note) (Pb-free) ISL6530CR Lead 5x5 QFN ISL6530CRZ Lead 5x5 QFN (See Note) (Pb-free) ISL6530EVAL1, 2 Evaluation Board * Add “ ...

  • Page 2

    Pinouts 24 LEAD (SOIC) TOP VIEW 24 UGATE1 1 23 BOOT1 2 22 PHASE1 3 21 VREF 4 20 FB1 COMP1 18 7 SENSE1 17 VREF_IN GNDA 15 PHASE2 BOOT2 13 ...

  • Page 3

    Block Diagram PGOOD FB1 COMP1 SENSE1 VREF_IN + VREF - FB2 COMP2 SENSE2 V2_SD 3 ISL6530 OCSET/SD VCC POWER-ON RESET (POR) + SOFT- - 40µA START OVER- CURRENT PWM ERROR COMPARATOR AMP INHIBIT + + - - PWM 0.8V REFERENCE ...

  • Page 4

    Typical Application +5V R OCSET OCSET/SD RESET GNDA SLEEP V2_SD VREF_IN V REF (.5xV ) DDQ VREF COMP1 FB1 R FB1 SENSE1 4 ISL6530 PGOOD VCC PGOOD BOOT1 UGATE1 PHASE1 PVCC1 LGATE1 PGND1 ISL6530 BOOT2 UGATE2 PHASE2 LGATE2 PGND2 COMP2 ...

  • Page 5

    Absolute Maximum Ratings Supply Voltage +7.0V CC ...

  • Page 6

    Functional Pin Description 24 LEAD (SOIC) TOP VIEW 24 UGATE1 1 23 BOOT1 2 22 PHASE1 3 21 VREF 4 20 FB1 COMP1 18 7 SENSE1 17 VREF_IN GNDA 15 PHASE2 ...

  • Page 7

    While the V supply “floats” held to about 50 via a low current window regulator which drives V DDQ via the SENSE2 pin. The window regulator can overcome least ±10mA of leakage ...

  • Page 8

    TIME FIGURE 2. SOFT-START INTERVAL Shoot-Through Protection A shoot-through condition occurs when both the upper MOSFET and lower MOSFET are turned on simultaneously, effectively shorting the input voltage to ground. To protect the regulators from ...

  • Page 9

    One method that may be employed to bypass the internal V reference generation is to supply an external reference TT directly to the V pin. When doing this the SENSE1 pin REF_IN must remain unconnected. Caution must be exercised when ...

  • Page 10

    To avoid over-current tripping in the DS(ON) normal operating load range, find the R the equation above with: 1. The maximum r at the highest junction temperature. DS(ON) 2. The minimum I from the specification table. OCSET > ...

  • Page 11

    Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the GATE pins to the MOSFET gates should be kept ...

  • Page 12

    DRIVER OSC PWM COMPARATOR - DRIVER DV + OSC E REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS COMP ISL6530 REFERENCE FIGURE 8. VOLTAGE-MODE ...

  • Page 13

    Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function ...

  • Page 14

    Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air ...

  • Page 15

    ISL6530 DC-DC Converter Application Circuit Figure 11 shows an application circuit for a DDR SDRAM power supply, including V (+2.5V) and V DDQ Detailed information on the circuit, including a complete Bill- V2_SD PGOOD VREF VREF_IN C 30 100pF GNDA ...

  • Page 16

    Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α µ 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in ...

  • Page 17

    ... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...