ISL6530CBZ-T Intersil, ISL6530CBZ-T Datasheet - Page 17

IC CONTROLLER INTEL 24SOIC

ISL6530CBZ-T

Manufacturer Part Number
ISL6530CBZ-T
Description
IC CONTROLLER INTEL 24SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6530CBZ-T

Applications
Controller, Intel Pentium® III, IV
Voltage - Input
4.5 ~ 5.5 V
Number Of Outputs
2
Voltage - Output
2.5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISL6530CBZ-TTR
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
For information regarding Intersil Corporation and its products, see www.intersil.com
17
ISL6530
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
NOTES:
10. Depending on the method of lead termination at the edge of the
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
6. The configuration of the pin #1 identifier is optional, but must be
7. Dimensions D2 and E2 are for the exposed pads which provide
8. Nominal dimensions are provided to assist with PCB Land Pattern
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
SYMBOL
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
improved electrical and thermal performance.
Design efforts, see Intersil Technical Brief TB389.
Anvil singulation method is used and not present for saw
singulation.
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
A1
A2
A3
D1
D2
E1
E2
Nd
Ne
L1
A
D
E
N
P
b
e
k
L
θ
0.80
0.18
2.95
2.95
0.25
0.30
MIN
8
-
-
-
-
-
MILLIMETERS
NOMINAL
5.00 BSC
5.00 BSC
4.75 BSC
0.20 REF
4.75 BSC
0.50 BSC
0.90
0.23
3.10
3.10
0.40
32
8
8
-
-
-
-
-
-
MAX
1.00
0.05
1.00
0.30
3.25
3.25
0.50
0.15
0.60
12
-
November 15, 2004
Rev. 1 10/02
NOTES
FN9052.2
5,8
7,8
7,8
10
9
9
9
9
8
2
3
3
9
9
-
-
-
-
-
-

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