ISL6530CBZ-T Intersil, ISL6530CBZ-T Datasheet - Page 6

IC CONTROLLER INTEL 24SOIC

ISL6530CBZ-T

Manufacturer Part Number
ISL6530CBZ-T
Description
IC CONTROLLER INTEL 24SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6530CBZ-T

Applications
Controller, Intel Pentium® III, IV
Voltage - Input
4.5 ~ 5.5 V
Number Of Outputs
2
Voltage - Output
2.5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISL6530CBZ-TTR
Functional Pin Description
BOOT1 and BOOT2
These pins provide bias voltage to the upper MOSFET
drivers. A single capacitor bootstrap circuit may be used to
create a BOOT voltage suitable to drive a standard N-
Channel MOSFET.
UGATE1 and UGATE2
Connect UGATE1 and UGATE2 to the corresponding upper
MOSFET gate. These pins provide the gate drive for the
upper MOSFETs. UGATE2 is also monitored by the adaptive
shoot through protection to determine when the upper FET
of the V
LGATE1 and LGATE2
Connect LGATE1 and LGATE2 to the corresponding lower
MOSFET gate. These pins provide the gate drive for the
lower MOSFETs. These pins are monitored by the adaptive
shoot through protection to determine when the lower FET
has turned off.
PGND1 and PGND2
These are the power ground connections for the gate drivers
of the PWM controllers. Tie these pins to the ground plane
through the lowest impedence connection available.
OCSET/SD
A resistor (R
the upper MOSFET of the V
overcurrent trip point. R
source (I
TT
OCS
regulator has turned off.
VREF_IN
PHASE1
PHASE2
UGATE2
UGATE1
SENSE1
OCSET
COMP1
BOOT2
), and the upper MOSFET on-resistance
BOOT1
GNDA
VREF
FB1
) connected from this pin to the drain of
10
12
11
1
2
3
4
5
7
8
9
6
24 LEAD (SOIC)
OCSET
TOP VIEW
DDQ
6
, an internal 40µA current
regulator sets the
24
23
22
21
20
19
18
17
16
15
14
13
PGND1
LGATE1
PVCC1
OCSET/SD
V2_SD
PGOOD
COMP2
SENSE2
FB2
VCC
LGATE2
PGND2
ISL6530
(r
point according to the following equation:
I
An overcurrent trip cycles the soft-start function.
Pulling the OCSET/SD pin to ground resets the ISL6530 and
all external MOSFETS are turned off allowing the two output
voltage power rails to float.
PGOOD
A high level on this open-drain output indicates that both the
V
voltage ranges.
GNDA
Signal ground for the IC. Tie this pin to the ground plane
through the lowest impedence connection available.
VCC
The 5V bias supply for the chip is connected to this pin. This
pin is also the positive supply for the lower gate driver,
LGATE2. Connect a well decoupled 5V supply to this pin.
V2_SD
A high level on the V2_SD input places the V2 controller into
“sleep” mode. In sleep mode, both UGATE2 and LGATE2
are driven low, effectively floating the V
PHASE 1
VREF_IN
PEAK
SENSE1
COMP1
DS(ON)
DDQ
GNDA
GNDA
VREF
FB1
=
and V
) set the V
I
------------------------------------------- -
1
2
3
4
5
6
7
8
OCS
r
TT
32
DS ON
9
R
regulators are within normal operating
(
OCSET
10
31
DDQ
)
11
30
32 LEAD (QFN)
converter over-current (OC) trip
TOP VIEW
12
29
13
28
14
27
TT
15
26
supply.
16
25
November 15, 2004
24
23
22
21
20
19
18
17
PVCC1
OCSET/SD
V2_SD
PGOOD
COMP2
SENSE2
FB2
VCC
FN9052.2

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