ISL6556ACBZ-T Intersil, ISL6556ACBZ-T Datasheet
ISL6556ACBZ-T
Specifications of ISL6556ACBZ-T
Related parts for ISL6556ACBZ-T
ISL6556ACBZ-T Summary of contents
Page 1
... VID setting. The ISL6556A uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. Ordering Information PART NUMBER* TEMP. (°C) PACKAGE ISL6556ACB SOIC ISL6556ACBZ SOIC (Note) (Pb-free) ISL6556ACR 5x5B QFN L32.5x5B ISL6556ACRZ 5x5B QFN ...
Page 2
Pinouts 32 LEAD QFN TOP VIEW VID3 1 2 VID2 VID1 3 VID0 4 5 VID12.5 6 OFS DAC 7 REF ISL6556A PWM4 ...
Page 3
ISL6565ACR Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET OFSOUT REF DAC VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB 3 ISL6556A OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT START ...
Page 4
Typical Application of ISL6556ACB +5V COMP VCC FB DAC VDIFF VSEN REF RGND PGOOD OVP ISEN1 ISL6556ACB VID4 PWM1 VID3 PWM2 VID2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 GND VID_PGOOD (BUFFERED) 4 ISL6556A ...
Page 5
Typical Application of ISL6556ACR +5V FB COMP VCC EN VDIFF DAC VSEN RGND REF PGOOD OVP OFSOUT ISL6556ACR VID4 ISEN1 VID3 PWM1 VID2 PWM2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 ENLL EN GND R T VID_PGOOD ...
Page 6
ISL6565ACB Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET REF DAC VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB 6 ISL6556A OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT START CLOCK ...
Page 7
Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V ...
Page 8
Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), T Unless Otherwise Specified. (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS pin OSCILLATOR Accuracy Adjustment Range Sawtooth Amplitude Max Duty Cycle ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth ...
Page 9
... Dynamic VID™ operations. PWM1, PWM2, PWM3, PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation ...
Page 10
OFSOUT (ISL6556ACR only) OFSOUT is the output of the offset-current generating circuit. It must be connected either to REF (recommended generate a dc offset. OVP Overvoltage protection pin. This pin pulls to VCC and is latched when ...
Page 11
RMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three- phase converter. INPUT-CAPACITOR CURRENT, 10A/DIV CHANNEL 3 Channel 3 INPUT CURRENT input current 10A/DIV ...
Page 12
... ISL6556A to include the combined tolerances of each of these elements. PWM1 The output of the error amplifier, V sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry that controls Σ ...
Page 13
VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote-sense output, V connected to the inverting input of the error amplifier through an external resistor. A digital to analog converter (DAC) generates a reference voltage based on ...
Page 14
Load-Line Regulation Some microprocessor manufacturers require a precisely- controlled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can be level ...
Page 15
... It is important that the driver ICs reach their POR level before the ISL6556A becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6556A with the HIP660X family of Intersil MOSFET drivers, which require (EQ. 9) 12V bias. 3. (ISL6556ACR only) The voltage on ENLL must be logic high to enable the controller ...
Page 16
Soft-Start During soft start, the DAC voltage ramps linearly from zero to the programmed VID level. The PWM signals remain in the high-impedance state until the controller detects that the ramping DAC level has reached the output-voltage level. This protects ...
Page 17
... VSEN falls below 0.6V with valid VCC or 1.5V otherwise. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. The PWM outputs remain low until VDIFF falls to the programmed DAC level when they enter a high-impedance state ...
Page 18
MOSFETs, inductors and heat-dissipating surfaces. MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate ...
Page 19
---------- ΔT ISEN 2 , ISEN 1 the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 18 is usually sufficient, it may occasionally be necessary to adjust R two ...
Page 20
V the peak-to-peak sawtooth signal amplitude as described in Figure 4 and Electrical Specifications. Once selected, the compensation values in Equations 21 assure a stable converter with reasonable transient performance. In most cases, ...
Page 21
Output Filter Design. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. 1000 100 10 10 100 SWITCHING FREQUENCY (kHz) FIGURE 13 SWITCHING FREQUENCY T Switching frequency is ...
Page 22
0.5 I L, 0.75 I L,PP O L,PP 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V O FIGURE 16. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY ...
Page 23
... Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals ...
Page 24
Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
Page 25
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...