ISL6334ACRZ Intersil, ISL6334ACRZ Datasheet
ISL6334ACRZ
Specifications of ISL6334ACRZ
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ISL6334ACRZ Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. FN6482.1 ...
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... IRZ ISL6334CRZ* ISL6334 CRZ ISL6334ACRZ* 6334A CRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... ISL6614, ISL6614A 12V Quad ISL6610, ISL6610A 5V Quad NOTE: Note: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous Channels. 3 ISL6334, ISL6334A COMMENTS DIODE GATE DRIVE ...
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ISL6334 and ISL6334A Block Diagram VDIFF - RGND X1 + VSEN SOFT-START + OVP - FAULT LOGIC +175mV SS VID7 VID6 VID5 DYNAMIC VID4 VID VID3 D/A VID2 VID1 VID0 DAC OFS OFFSET REF FB COMP 1.11V + OCP - ...
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Typical Application: 4-Phase VR with Integrated Thermal Compensation, PSI# (DE and GVOT) +5V COMP VCC DAC FB REF VDIFF VSEN PWM1 RGND ISEN1- EN_VTT VTT ISEN1+ VR_RDY VID7 ISL6334 ISL6334 VID6 VID5 VID4 PWM2 VID3 VID2 ISEN2- VID1 ISEN2+ VID0 ...
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Typical Application - 4-Phase VR with 1-Phase PSI# and without Diode Emulation and GVOT) +5V COMP VCC FB VDIFF VSEN PWM1 RGND ISEN1- EN_VTT VTT ISEN1+ VR_RDY VID7 ISL6334 ISL6334A VID6 VID5 VID4 PWM2 VID3 VID2 ISEN2- VID1 ISEN2+ VID0 ...
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Typical Application -VR with External Thermal Compensation, 2-Phase PSI# (no DE and GVOT) NTC + COMP VCC FB VDIFF VSEN RGND ISEN1+ EN_VTT VTT ISEN1- VR_RDY PWM1 VID7 VID6 ISL6334 ISL6334A VID5 VID4 VID3 PWM3 VID2 ISEN3- VID1 ...
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... Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature ISL6334ACRZ, ISL6334CRZ . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6334IRZ, ISL6334AIRZ .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. ...
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Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Max DAC Sink Current ...
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Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER THERMAL MONITORING AND FAN ...
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... PWM1, PWM2, PWM3, PWM4 - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM2, PWM3 and PWM4. Tie PWM2 to VCC to configure for 1-phase operation. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation ...
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Inactive channels should have their respective current sense inputs left open (for example, open ISEN4+ and ISEN4- for 3-phase operation). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie ...
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... Figure 21 shows the single phase input-capacitor RMS current for comparison. PWM Modulation Scheme The ISL6334, ISL6334A adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads ...
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... The matching driver's internal PWM resistor divider can further raise the PWM potential, but not lower it below the level set by the controller IC. Therefore, the controller's PWM outputs are directly compatible with Intersil drivers that require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM signal amplitudes are generally incompatible. ...
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... Channel current balance is achieved by T comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil’s patented current-balance method. (EQ. 6) Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area ...
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... The output of the error amplifier, V COMP sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry, which control voltage regulation, are illustrated in Figure 6. ...
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TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
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TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
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By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a ...
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... POR level before the ISL6334, ISL6334A becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6334, ISL6334A with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR ...
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... At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns). This causes the (EQ. 17) Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC plus 75mV, PWM ...
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... IMON to GND. At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns, commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft-start ...
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VCC R 0.391V CC TM1 NTC 0.333V CC FIGURE 12. BLOCK DIAGRAM OF THERMAL MONITORING FUNCTION 100 TEMPERATURE (°C) FIGURE 13. THE RATIO ...
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Based on VCC voltage, ISL6334, ISL6334A converts the TM pin voltage to a 6-bit TM digital signal for temperature compensation. With the non-linear A/D converter of ISL6334, ISL6334A, the TM digital signal is linearly proportional to the NTC temperature. For ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs, which include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
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Select values for these resistors by using Equation 30 OCP R = -------------------------- - ------------- - ISEN – × 105 10 where R is the ...
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C (OPTIONAL COMP DROOP - VDIFF FIGURE 17. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6334, ISL6334A CIRCUIT The feedback resistor has already been chosen as FB outlined in “Load-Line ...
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The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 30 ...