ISL6262CRZ Intersil, ISL6262CRZ Datasheet - Page 17

• Manufacturer Part Number: ISL6262CRZ
• Description: IC CORE REG 2PHASE 48-QFN
• Manufacturer: Intersil

Specifications of ISL6262CRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into automatic-DCM or forced-
CCM mode, the timing is carefully adjusted to eliminate
output voltage excursions. When a phase is added, the
current balance between phases is quickly restored.
While PSI# is high, both phases are switching. If PSI# is
asserted low and either DPRSTP# or DPRSLPVR are not
asserted, the controller will transition to CCM operation with
only phase 1 switching, and both FET's of phase 2 will be off.
The controller will thus eliminate switching losses associated
with the unneeded channel.
When PSI#, DPRSTP#, and DPRSLPVR are all asserted,
the controller will transition to single-phase DCM mode. In
this mode, both FET's associated with phase 2 will be off,
Overcurrent fault
Way-Overcurrent fault
Overvoltage fault (1.7V)
Overvoltage fault (+200mV)
Undervoltage fault
(-300mV)
Unbalance fault
(7.5mV)
Over-temperature
fault (NTC <1.18V)
FIGURE 29. DEEPER SLEEP TRANSITION SHOWING
V
OUT
& V
SOFT
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
DPRSLPVR
VID #
-2.5mV/µs
17
2.5mV/µs
FAULT DURATION PRIOR
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262
TO PROTECTION
Immediately
Immediately
120µs
<2µs
1ms
1ms
1ms
10mV/µs
ISL6262
PWM1, PWM2 three-state,
PGOOD latched low
PWM1, PWM2 three-state,
PGOOD latched low
Low-side FET on until Vcore
<0.85V, then PWM three-state,
PGOOD latched low (OV-1.7V
always)
PWM1, PWM2 three-state,
PGOOD latched low
PWM1, PWM2 three-state,
PGOOD latched low
PWM1, PWM2 three-state,
PGOOD latched low
VR_TT# goes low
and the ISL6262 will turn-off the lower FET of channel 1
whenever the channel 1 current decays to zero. As load is
further reduced, the phase 1 channel switching frequency
will decrease, thus maintaining high efficiency.
Dynamic Operation
Refer to Figure 29, the ISL6262 responds to changes in VID
command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
With C
voltage will move at ±2.8mV/s for large changes in voltage.
For DPRSLPVR LOW, the large signal dV/dt will be
±13mV/s. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
Keeping DPRSLPVR HIGH for voltage transitions into and
out of Deeper Sleep will result in low dV/dt output voltage
changes with resulting minimized audio noise. For fastest
recovery from Deeper Sleep to Active mode, holding
DPRSLPVR LOW will result in maximum dV/dt. Therefore,
the ISL6262 is IMVP-6 compliant for DPRSTP# and
DPRSLPVR logic.
Intersil's R
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6262 will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
Protection
The ISL6262 provides overcurrent, overvoltage, under-
voltage protection and over-temperature protection as
shown in Table 3.
PROTECTION ACTIONS
SOFT
3
Technology™ has intrinsic voltage feedforward.
= 15nF and DPRSLPVR HIGH, the output
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
N/A
FAULT RESET
May 15, 2006
FN9199.2