ISL6262CRZ Intersil, ISL6262CRZ Datasheet - Page 22

• Manufacturer Part Number: ISL6262CRZ
• Description: IC CORE REG 2PHASE 48-QFN
• Manufacturer: Intersil

Specifications of ISL6262CRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

whether Equation 9 or Equation 10 can accurately represent
the NTC resistor value at the designed temperature range.
Therefore, the NTC branch is designed to have a 470k NTC
and 4.02k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
thermistor should be placed in the spot which gives the best
indication of the temperature of voltage regulator circuit. The
actual hysteresis temperature is about 105°C and 97°C.
Static Mode of Operation - Static Droop Using DCR
Sensing
As previously mentioned, the ISL6262 has an internal
differential amplifier which provides for very accurate voltage
regulation at the die of the processor. The load line
regulation is also accurate for both two-phase and single-
phase operation. The process of selecting the components
for the appropriate load line droop is explained here.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
The two-phase solution using DCR sensing is shown in
Figure 31. There are two resistors connecting to the
terminals of inductor of each phase. These are labeled RS
and RO. These resistors are used to obtain the DC voltage
drop across each inductor. Each inductor will have a certain
level of DC current flowing through it, and this current when
multiplied by the DCR of the inductor creates a small DC
voltage drop across the inductor terminal. When this voltage
is summed with the other channels DC voltages, the total DC
load current can be derived.
RO is typically 1 to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
OC
VDIFF
INTERNAL TO
ISL6262
-
+
+
+
10µA
FIGURE 34. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
1
1
+
+
-
-
22
RTN
VSEN
DROOP
-
+
DROOP
OCSET
VSUM
DFB
VO'
ISL6262
Cn
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 34.
Figure 34 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by:
For the convenience of analysis, the NTC network
comprised of Rntc, Rseries and Rpar, given in Figure 31, is
labelled as a single resistor Rn in Figure 34.
The first step in droop load line compensation is to adjust
Rn, RO
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb we start with the voltage drop across the
Rn network, VN, to be 0.5-0.8 times V
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by
For simplicity, the gain of Vn to the V
G1, also dependent on the temperature of the NTC
thermistor.
VSUM
V
R
VN
VO'
DCR_EQU
n
+
-
T ( )
=
EQV
(
--------------------------------------------------------------
R
R
Rn
series
series
=
and RS
I
-------------------------------- -
=
OUT
(
--------------------------------------------------------------------
(
+
+
Rntc
Rntc
R
R
RS
•
2
EQV
ntc
ntc
DCR
EQV
+
+
Vdcr
) R
+
RO
Rseries
Rseries
•
such that sufficient droop voltage
R
par
=
EQV
par
EQV
RS
--------
2
)
)
=
=
×
+
RO
-------- -
I
Rpar
Rpar
OUT
2
dcr_equ
DCR_EQU
×
DCR
-------------
2
is defined by
. This ratio
May 15, 2006
(EQ. 14)
(EQ. 15)
FN9199.2