ISL6262AIRZ Intersil, ISL6262AIRZ Datasheet
ISL6262AIRZ
Specifications of ISL6262AIRZ
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ISL6262AIRZ Summary of contents
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... ISL6262ACRZ ISL6262ACRZ-T* ISL6262 ACRZ -10 to +100 48 Ld 7x7 QFN L48.7x7 ISL6262AIRZ ISL6262AIRZ-T* ISL6262 AIRZ *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Pinout 1 PGOOD 2 PSI# 3 PMON 4 RBIAS VR_TT NTC 7 SOFT 8 OCSET VW 9 COMP FB2 12 2 ISL6262A ISL6262A (48 LD 7x7 QFN) TOP VIEW ...
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... INPUT POWER SUPPLY +5V Supply Current +3.3V Supply Current Battery Supply Current at VIN pin POR (Power-On Reset) Threshold SYSTEM AND REFERENCES System Accuracy (V ISL6262ACRZ System Accuracy (V ISL6262AIRZ Droop Amplifier Offset R Voltage BIAS Boot Voltage Maximum Output Voltage VID Off State 3 ISL6262A Thermal Information Thermal Resistance (Typical) QFN Package (Notes 1, 2) ...
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Electrical Specifications tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range AMPLIFIERS Droop Amplifier Offset Error Amp DC Gain ...
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Electrical Specifications tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER PGOOD Delay Overvoltage Threshold Severe Overvoltage Threshold OCSET Reference Current OC Threshold Offset Current Imbalance ...
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ISL6262A Gate Driver Timing Diagram PWM t PDHU UGATE 1V LGATE t FL Functional Pin Description PGOOD 1 PSI PMON 4 RBIAS VR_TT NTC 7 SOFT 8 OCSET VW 9 COMP FB2 12 ...
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PGOOD - Power good open-drain output. Connect externally with 680Ω to VCCP or 1.9kΩ to 3.3V. PSI# - Current indicator input. When asserted low, indicates a reduced load-current condition and initiates single-phase operation. PMON - Analog output. PMON is proportional ...
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Functional Block Diagram 6µA 54µA PVCC PVCC VDD 1.2V VIN VIN ISEN2 CURRENT BALANCE ISEN1 3V3 PGOOD PGOOD MONITOR CLK_EN# AND LOGIC P FLT GOOD FAULT AND PGOOD LOGIC RBIAS DAC FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6262A 8 ...
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Typical Performance Curves 100 12. 19. (A) OUT FIGURE 2. ACTIVE MODE EFFICIENCY, ...
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Typical Performance Curves V SOFT VR_ON FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE OF 2.5mV/µs AT VID = 1V 1.4375V OUT V @ 1.2V OUT PGD_IN CLK_EN# FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN# AND IMVP-6+ PGOOD I ...
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Typical Performance Curves V OUT FIGURE 14. LOAD STEP-UP RESPONSE AT THE CPU SOCKET MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE CCM V OUT FIGURE 16. LOAD DUMP RESPONSE AT THE CPU SOCKET MPGA479, 35A LOAD STEP @ 200A/µs, ...
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Typical Performance Curves DPRSLPVR V OUT PHASE1 PHASE2 FIGURE 20. C4 ENTRY WITH VID CHANGE 0011X00 FROM 1.2V TO 1.15V 2A, TRANSITION OF LOAD 2-CCM TO 1-DCM, PSI# TOGGLE FROM WITH DPRSLPVR FROM 0 TO ...
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Typical Performance Curves V Vcore CORE PMON AFTER 40kHz FILTER PMON after 40 kHz filter FIGURE 26. VID TRANSITION FROM 1V TO 1.15V I EXTERNAL FILTER 40kΩ AND 100pF AT PMON PMON PMON PMON AFTER 40kHZ FILTER PMON after 40 ...
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Simplified Application Circuit for DCR Current Sensing V +3 VR_TT VID<0:6> DPRSTP# DPRSLPVR PSI# CLK_ENABLE# VR_ON IMVP-6+_PWRGD REMOTE SENSE ...
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Simplified Application Circuit for Resistive Current Sensing V +3 VR_TT VID<0:6> DPRSTP# DPRSLPVR PSI# CLK_ENABLE# VR_ON IMVP-6+_PWRGD REMOTE SENSE ...
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... DCM-mode operation. 3 The heart of the ISL6262A is R Technology™, Intersil’s Robust Ripple Regulator modulator. The R combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. The ISL6262A modulator internally ...
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This voltage is used as an input to a differential amplifier to achieve the IMVP-6+ load line, and also as the input to the overcurrent protection circuit. When using inductor DCR current sensing, a ...
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... DPRSLPVR LOW results in maximum dV/dt. Therefore, the 10mV/µs ISL6262A is IMVP-6+ compliant for DPRSTP# and DPRSLPVR logic. Intersil result, high-speed input voltage steps do not result in significant output voltage perturbations. In response to load current step increases, the ISL6262A will transiently raise the switching frequency so that response time is decreased and current is shared by two channels ...
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For overloads exceeding 2.5xthe set level, the PWM outputs will immediately shut off and PGOOD goes low to maximize protection due to hard shorts. In addition, excessive phase unbalance (for example, due to gate driver failure) will be detected in ...
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... To achieve optimum performance, place common mode and differential mode filters to analog ground on VSEN and RTN as shown in Figure 37. Intersil recommends the use of the R connected to V These resistors provide voltage feedback in the event that the system is powered up without a processor installed. ...
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ISEN1 ISEN2 ISEN2 ISEN1 10µA OCSET - OC + VSUM + DROOP DFB INTERNAL TO - ISL6262A DROOP + VSEN RTN VDIFF 330pF 0.01µF R 330pF VCC_SENSE R OPN2 FIGURE 37. SIMPLIFIED SCHEMATIC ...
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The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature goes down, the NTC thermistor voltage ...
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OC + DROOP INTERNAL TO ISL6262A + VDIFF RTN VSEN FIGURE 40. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING thermistor should be placed in the spot which gives ...
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... Do not let the mismatch get larger than 600Ω. To reduce the mismatch, multiply both R factor. The appropriate factor in the example is (EQ. 24) 1404/853 = 1.65. In summary, the predicted load line with the designed droop network parameters based on the Intersil design tool is shown in Figure 41 (EQ. 25) 84mV ( ) Rdrp1 --------------- - Rdrp1 ...
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INDUCTOR TEMPERATURE (°C) FIGURE 41. LOAD LINE PERFORMANCE WITH NTC THERMAL COMPENSATION Dynamic Mode of Operation - Dynamic Droop Using DCR Sensing Droop is very important for load transient performance. ...
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... If the PC board trace resistance from the inductor to the microprocessor are significantly different between two phases, the current will not be balanced perfectly. Intersil has a proprietary method to achieve the perfect current sharing in case of severe unbalanced layout. When choosing the current sense resistor, both the tolerance of the resistance and the TCR are important. Also, the current sense resistor’ ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ...