ISL6262IRZ-T Intersil, ISL6262IRZ-T Datasheet
ISL6262IRZ-T
Specifications of ISL6262IRZ-T
Related parts for ISL6262IRZ-T
ISL6262IRZ-T Summary of contents
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... ISL6262CRZ-T (Note) ISL6262IRZ (Note) ISL6262IRZ-T (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil ...
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Pinout 1 PGOOD 2 PSI# 3 PGD_IN 4 RBIAS VR_TT NTC 7 SOFT 8 OCSET VW 9 COMP FB2 12 2 ISL6262 ISL6262 (7x7 QFN) TOP VIEW ...
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... PARAMETER INPUT POWER SUPPLY +5V Supply Current +3.3V Supply Current Battery Supply Current at VIN pin POR (Power-On Reset) Threshold SYSTEM AND REFERENCES System Accuracy ISL6262CRZ ISL6262IRZ RBIAS Voltage Boot Voltage Maximum Output Voltage V V VID Off State CHANNEL FREQUENCY Nominal Channel Frequency ...
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... I SNK(LGATE) UGATE to PHASE Resistance GATE DRIVER SWITCHING TIMING (refer to timing diagram) UGATE Turn-On Propagation Delay ISL6262CRZ ISL6262IRZ LGATE Turn-On Propagation Delay ISL6262CRZ ISL6262IRZ BOOTSTRAP DIODE Forward Voltage Leakage POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current 4 ISL6262 = -40°C to 100°C, Unless Otherwise Specified. (Continued) ...
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... Electrical Specifications PARAMETER PGOOD Delay ISL6262CRZ ISL6262IRZ Overvoltage Threshold Severe Overvoltage Threshold OCSET Reference Current OC Threshold Offset Current Imbalance Threshold Undervoltage Threshold (VDIFF-SOFT) LOGIC INPUTS VR_ON, DPRSLPVR and PGD_IN Input Low VR_ON, DPRSLPVR and PGD_IN Input High Leakage Current of VR_ON and ...
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ISL6262 Gate Driver Timing Diagram PWM t PDHU UGATE 1V LGATE t FL Functional Pin Description PGOOD 1 PSI PGD_IN 4 RBIAS VR_TT NTC 7 SOFT 8 OCSET VW 9 COMP FB2 12 ...
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SOFT - A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The SOFT pin is the non-inverting input of the error amplifier. OCSET - Overcurrent set input. A resistor from this pin ...
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Functional Block Diagram 6µA 54µA PVCC PVCC VDD 1.18V VIN VIN ISEN2 CURRENT BALANCE ISEN1 3V3 PGOOD PGOOD MONITOR CLK_EN# AND LOGIC PGD_IN P FLT GOOD FAULT AND PGOOD LOGIC RBIAS DAC FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6262 ...
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Typical Performance Curves 100 12. 19. (A) OUT FIGURE 2. ACTIVE MODE EFFICIENCY, ...
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Typical Performance Curves V SOFT VR_ON FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE OF 2.5mV/µs AT VID = 1V 1.4375V OUT V @ 1.2V OUT PGD_IN IMVP-6_PWRGD CLK_EN# FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN# AND IMVP-6 PGOOD ...
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Typical Performance Curves V OUT FIGURE 14. LOAD STEP-UP RESPONSE VIA CPU SOCKET MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE CCM V OUT FIGURE 16. LOAD DUMP RESPONSE VIA CPU SOCKET MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE ...
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Typical Performance Curves DPRSLPVR V OUT PHASE1 PHASE2 FIGURE 20. C4 ENTER WITH VID CHANGE 0011X00 FROM 1.2V TO 1.15V 2A, TRANSITION OF LOAD 2-CCM TO 1-DCM, PSI# TOGGLE FROM WITH DPRSLPVR FROM 0 TO ...
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Simplified Application Circuit for DCR Current Sensing V +3 VR_TT VID<0:6> DPRSTP# DPRSLPVR PSI# MCHOK CLK_ENABLE# VR_ON IMVP-6_PWRGD REMOTE SENSE ...
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Simplified Application Circuit for Resistive Current Sensing V +3 VR_TT VID<0:6> DPRSTP# DPRSLPVR PSI# MCHOK CLK_ENABLE# VR_ON IMVP-6_PWRGD REMOTE SENSE ...
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... DCM-mode operation. 3 The heart of the ISL6262 is R Technology™, Intersil’s Robust Ripple Regulator modulator. The R combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. The ISL6262 modulator internally synthesizes ...
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Figure 26. In both cases signals representing the inductor currents are summed at VSUM, which is the non-inverting input to the DROOP amplifier shown in the block diagram of ...
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... Deeper Sleep to Active mode, holding DPRSLPVR LOW will result in maximum dV/dt. Therefore, the ISL6262 is IMVP-6 compliant for DPRSTP# and DPRSLPVR logic. Intersil result, high-speed input voltage steps do not result in significant output voltage perturbations. In response to load current step increases, the ISL6262 will transiently raise the switching frequency so that response time is decreased and current is shared by two channels ...
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Overcurrent protection is tied to the voltage droop which is determined by the resistors selected as described in the “Component Selection and Application” section. After the load-line is set, the OCSET resistor can be selected to detect overcurrent at any ...
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SLEWRATE, as given in the IMVP-6 specification will determine the choice of the SOFT capacitor, C following equation ----------------------------------- - C = SOFT SLEWRATE Using a SLEWRATE of 10mV/µs, and the typical I given in the Electrical Specification ...
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ISEN1 ISEN2 ISEN2 ISEN1 10µA OCSET - OC + VSUM + DROOP DFB INTERNAL TO - ISL6262 DROOP + VSEN RTN VDIFF 82nF 10 0.018µF R 0.018µF VCC_SENSE R OPN2 FIGURE 31. SIMPLIFIED ...
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When temperature increases, the NTC resistor value on NTC pin decreases. Thus, the voltage on NTC pin decreases to a level lower than 1.18V. The comparator output changes polarity and turns SW1 off and connects SW2 to 1.20V. This pulls ...
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Equation 9 or Equation 10 can accurately represent the NTC resistor value at the designed temperature range. Therefore, the NTC branch is designed to have a 470k NTC and 4.02k resistor in series. The part number of the NTC ...
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... Do not let the mismatch get larger than 600Ω. To reduce the mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate factor. The appropriate factor in the example is (EQ. 22) 1392/853 = 1.632. In summary, the predicted load line with the designed droop network parameters based on the Intersil design tool is shown in Figure 35. 84mV ( ) Rdrp1 --------------- - Rdrp1 Rdrp2 ...
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INDUCTOR TEMPERATURE (°C) FIGURE 35. LOAD LINE PERFORMANCE WITH NTC THERMAL COMPENSATION Dynamic Mode of Operation - Dynamic Droop Using DCR Sensing Droop is very important for load transient performance. If ...
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In the above example, the two errors add to 4A. For the two phase DC/DC, the currents would be 22A in one phase and 18A in the other phase. In the above analysis, the current balance can be calculated with ...
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OCSET - DROOP INTERNAL TO - ISL6262 DROOP + VDIFF RTN VSEN FIGURE 36. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING 26 ISL6262 Voc - ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...