IC PWR SUPPLY DDR 28-TQFN

MAX8632ETI+T

Manufacturer Part NumberMAX8632ETI+T
DescriptionIC PWR SUPPLY DDR 28-TQFN
ManufacturerMaxim Integrated Products
MAX8632ETI+T datasheet
 


Specifications of MAX8632ETI+T

ApplicationsController, DDRVoltage - Input2 ~ 28 V
Number Of Outputs1Voltage - Output1.8V, 2.5V, 0.7 ~ 5.5 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case28-TQFN Exposed PadOutput Voltage1.8 V, 2.5 V, 0.7 V to 5.5 V
Output Current15 AInput Voltage2 V to 28 V
Mounting StyleSMD/SMTMaximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
Page 21/29

Download datasheet (822Kb)Embed
PrevNext
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
capacitor. Nevertheless, a ceramic capacitor of at least
10µF must be used and must be added and placed as
close as possible to the VTTI pin. This value must be
increased with larger load current, or if the trace from
the VTTI pin to the power source is long and has signifi-
cant impedance. Furthermore, to prevent undesirable
VTTI bounce from coupling back to the REFIN input
and possibly causing instability in the loop, the REFIN
pin should ideally tap its signal from a separate low-
impedance DC source rather than directly from the
VTTI input. If the latter is unavoidable, increase the
amount of bypass capacitance at the VTTI input and
add additional bypass at the REFIN pin.
MOSFET Selection (Buck)
The MAX8632 drives external, logic-level, n-channel
MOSFETs as the circuit-switch elements. The key
selection parameters:
On-resistance (R
): the lower, the better.
DS(ON)
Maximum drain-to-source voltage (V
at least 20% higher than input supply rail at the high-
side MOSFET’s drain.
Gate charges (Q
, Q
, Q
): the lower the better.
G
GD
GS
Choose MOSFETs with rated R
DS(ON)
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to its switching loss at nominal input voltage
and maximum output current (see below). For the low-
side MOSFET, make sure that it does not spuriously
turn on because of dV/dt caused by the high-side
MOSFET turning on, as this results in shoot-through
current degrading efficiency. MOSFETs with a lower
Q
to Q
ratio have higher immunity to dV/dt.
GD
GS
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the low-side MOSFET, the
worst case is at V
. For the high-side MOSFET,
IN(MAX)
the worst case could be at either V
The high-side MOSFET and low-side MOSFET have dif-
ferent loss components due to the circuit operation.
The low-side MOSFET operates as a zero-voltage
switch; therefore, major losses are:
• The channel-conduction loss (P
• The body-diode conduction loss (P
• The gate-drive loss (P
):
LSDR
V
OUT
=
 ×
P
1
-
I
LSCC
LOAD
V
IN
______________________________________________________________________________________
Use R
DS(ON)
where V
the dead time (≈30ns), and f
quency. Because of the zero-voltage switch operation,
the low-side MOSFET gate-drive loss occurs as a result
of charging and discharging the input capacitance,
(C
). This loss is distributed among the average DL
ISS
gate-driver’s pullup and pulldown resistance, R
(≈1Ω), and the internal gate resistance (R
MOSFET (≈2Ω). The drive power dissipated is given by:
P
LSDR
The high-side MOSFET operates as a duty-cycle control
): should be
DSS
switch and has the following major losses:
• The channel-conduction loss (P
• The VI overlapping switching loss (P
• The drive loss (P
at V
= 4.5V.
GS
(The high-side MOSFET does not have body-diode
conduction loss because the diode never conducts
current):
Use R
DS(ON)
P
HSSW
where I
determined by:
or V
.
IN(MIN)
IN(MAX)
where R
)
LSCC
tance (1Ω typ) and R
tance of the MOSFET (≈2Ω):
)
LSDC
P
HSDR
2
×
R
DS ON
(
)
at T
:
J(MAX)
=
×
×
×
P
2
I
V
t
LSDC
LOAD
F
DT
is the body-diode forward-voltage drop, t
F
is the switching fre-
SW
2
=
×
×
×
C
V
f
ISS
GS
SW
R
GATE
)
HSCC
HSSW
)
HSDR
V
2
OUT
=
×
×
P
I
R
HSCC
LOAD
DS ON
V
IN
at T
:
J(MAX)
Q
GS
=
×
×
×
V
I
f
IN
LOAD
SW
is the average DH-driver output current
GATE
2 5
.
V
=
I
GATE ON
(
)
+
R
R
DH
GATE
is the high-side MOSFET driver’s on-resis-
DH
is the internal gate resis-
GATE
R
=
×
×
×
Q
V
f
G
GS
SW
R
GATE
f
SW
is
DT
DL
) of the
GATE
R
GATE
+
R
DL
)
(
)
+
Q
GD
I
GATE
GATE
+
R
DH
21