MAX8632ETI+T Maxim Integrated Products, MAX8632ETI+T Datasheet - Page 21

IC PWR SUPPLY DDR 28-TQFN

MAX8632ETI+T

Manufacturer Part Number
MAX8632ETI+T
Description
IC PWR SUPPLY DDR 28-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX8632ETI+T

Applications
Controller, DDR
Voltage - Input
2 ~ 28 V
Number Of Outputs
1
Voltage - Output
1.8V, 2.5V, 0.7 ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TQFN Exposed Pad
Output Voltage
1.8 V, 2.5 V, 0.7 V to 5.5 V
Output Current
15 A
Input Voltage
2 V to 28 V
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
capacitor. Nevertheless, a ceramic capacitor of at least
10µF must be used and must be added and placed as
close as possible to the VTTI pin. This value must be
increased with larger load current, or if the trace from
the VTTI pin to the power source is long and has signifi-
cant impedance. Furthermore, to prevent undesirable
VTTI bounce from coupling back to the REFIN input
and possibly causing instability in the loop, the REFIN
pin should ideally tap its signal from a separate low-
impedance DC source rather than directly from the
VTTI input. If the latter is unavoidable, increase the
amount of bypass capacitance at the VTTI input and
add additional bypass at the REFIN pin.
The MAX8632 drives external, logic-level, n-channel
MOSFETs as the circuit-switch elements. The key
selection parameters:
On-resistance (R
Maximum drain-to-source voltage (V
at least 20% higher than input supply rail at the high-
side MOSFET’s drain.
Gate charges (Q
Choose MOSFETs with rated R
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to its switching loss at nominal input voltage
and maximum output current (see below). For the low-
side MOSFET, make sure that it does not spuriously
turn on because of dV/dt caused by the high-side
MOSFET turning on, as this results in shoot-through
current degrading efficiency. MOSFETs with a lower
Q
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the low-side MOSFET, the
worst case is at V
the worst case could be at either V
The high-side MOSFET and low-side MOSFET have dif-
ferent loss components due to the circuit operation.
The low-side MOSFET operates as a zero-voltage
switch; therefore, major losses are:
• The channel-conduction loss (P
• The body-diode conduction loss (P
• The gate-drive loss (P
GD
to Q
P
LSCC
GS
ratio have higher immunity to dV/dt.
=
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
G
1
DS(ON)
______________________________________________________________________________________
, Q
IN(MAX)
-
V
GD
MOSFET Selection (Buck)
OUT
V
IN
LSDR
, Q
): the lower, the better.
. For the high-side MOSFET,
 ×
GS
):
): the lower the better.
I
LOAD
DS(ON)
LSCC
IN(MIN)
LSDC
2
)
DSS
×
at V
R
)
): should be
DS ON
or V
GS
(
IN(MAX)
= 4.5V.
)
.
Use R
where V
the dead time (≈30ns), and f
quency. Because of the zero-voltage switch operation,
the low-side MOSFET gate-drive loss occurs as a result
of charging and discharging the input capacitance,
(C
gate-driver’s pullup and pulldown resistance, R
(≈1Ω), and the internal gate resistance (R
MOSFET (≈2Ω). The drive power dissipated is given by:
switch and has the following major losses:
• The channel-conduction loss (P
• The VI overlapping switching loss (P
• The drive loss (P
(The high-side MOSFET does not have body-diode
conduction loss because the diode never conducts
current):
Use R
where I
determined by:
where R
tance (1Ω typ) and R
tance of the MOSFET (≈2Ω):
The high-side MOSFET operates as a duty-cycle control
ISS
P
P
P
HSDR
HSSW
LSDR
). This loss is distributed among the average DL
DS(ON)
DS(ON)
GATE
F
P
P
DH
LSDC
HSCC
is the body-diode forward-voltage drop, t
=
=
is the high-side MOSFET driver’s on-resis-
=
at T
at T
I
is the average DH-driver output current
GATE ON
C
Q
V
ISS
IN
=
=
G
J(MAX)
J(MAX)
2
HSDR
(
V
×
×
I
×
LOAD
OUT
V
IN
I
V
V
LOAD
)
GATE
GS
:
:
GS
)
=
×
2
×
R
×
I
×
LOAD
DH
is the internal gate resis-
×
V
f
SW
SW
F
f
f
SW
SW
+
2 5
×
.
HSCC
2
is the switching fre-
R
×
V
×
×
GATE
t
×
DT
R
HSSW
R
R
Q
)
GATE
GATE
DS ON
GS
×
R
R
I
(
GATE
GATE
GATE
GATE
f
)
+
SW
+
+
)
Q
R
R
) of the
GD
DH
DL
DT
DL
21
is

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