L6731B STMicroelectronics, L6731B Datasheet
L6731B
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L6731B Summary of contents
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... High performance / high density DC-DC DS(on) modules ■ Low voltage distributed DC-DC ■ niPOL converters ■ DDR memory supply ■ DDR termination supply ■ Graphic cards Package HTSSOP16 HTSSOP16 Rev 3 L6731B Dedicated to DDR Memory HTSSOP16 (Exposed Pad) Packing Tube Tape & Reel 1/24 www.st.com 24 ...
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... Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.9 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.11 Minimum on-time (TON, MIN Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 L6731B ...
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... L6731B 1 Summary description The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPOL converters designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of ± ...
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... Summary description 1.1 Functional description Figure 1. Block Diagram OCL SS/INH Protection and Ref DDR- PGOOD + VTTREF 4/24 V =4.5V to14V CC OCH VCCDR VCC LDO Monitor OSC - L6731B - + 0. PWM E COMP V =1.8V to14V in BOOT HGATE PHASE LGATE PGND SGND VFB L6731B Vo ...
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... L6731B 2 Electrical data 2.1 Maximum rating Table 1. Absolute maximum ratings Symbol GND and PGND, OCH, PGOOD Boot Voltage BOOT - PHASE V V HGATE - PHASE V BOOT BOOT PHASE V PHASE PHASE Spike, transient < 50ns (F SS, FB, VTTREF, DDR-IN, SYNC, OCL, LGATE, COMP, V CCDR OCH Pin ...
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... V = 0.6V/F CCDR REF = 95%-100 CCDR -> REF VCC VCCDR LGATE PGND BOOT HGATE PHASE OCH input of the DDR memory itself. Filter to GND OUT =250KHz SW =500KHz SW = 0.6V/F =250KHz SW at 2.5V (typ.). The device captures the EAREF meets the UVLO threshold. CC L6731B through ...
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... L6731B Table 3. Pin functions A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100µ OCL 8 OCL Connecting a capacitor from this pin to GND helps in reducing the noise injected from ...
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... V Output Voltage FB 8/24 Test Condition OSC = open GND OSC= open open open, PH=open V = 1.7V OCH V = 1.7V OCH V =5.5V to 14V 1mA to 100mA 0. DIS th L6731B Min. Typ. Max. Unit 8.5 10 4.0 4.2 4.4 V 3.6 3.8 4.0 V 1.1 1.25 1.47 V 0.9 1.05 1. ...
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... L6731B Table 4. Electrical Characteristics Symbol Parameter Error Amplifier R EAREF Input Resistance EAREF I I.I. bias current FB Ext Ref Clamp V Error amplifier offset OFFSET G Open Loop Voltage Gain V GBWP Gain-Bandwidth Product SR Slew-Rate Gate Drivers R High Side Source Resistance HGATE_ON R High Side Sink Resistance ...
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... LDO during the recharge of the bootstrap capacitor. V also represents a voltage reference for PGOOD pin (see CCDR 10/24 Table 3. Pins function and section 4.3 Internal and external pin (Figure 3.). CCDR Figure 4. V L6731B this case V and CCDR CC pin must be filtered with at CCDR Table 3. Pins Function). ...
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... L6731B 5.3 Bypassing the LDO to avoid the voltage drop with low Vcc the internal LDO works in dropout with an output resistance of about 1 . The CC maximum LDO output current is about 100mA and so the output voltage drop is 100mV, to avoid this the LDO can be bypassed. Figure 4. ...
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... After that it becomes 10µA until the final charge value of approximately 4V (see Figure 6. Device start-up: Voltage at the SS pin 12/24 2.5V are above their turn-ON thresholds ( 0.6V/500KHz 0.6V/250KHz DDR-IN/2 250KHz Error Amplifier Ref. is monitored by the OCH pin) IN with an internal current generator. The Figure 6.). L6731B t t ...
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... SS MOSFET begins to switch and the output voltage starts to increase. The L6731B can always sink or source current over current is detected during the soft-start phase, the device provides a constant-current-protection. In this way, in case of short soft-start time and/or small ...
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... Even if the device doesn't report an over-voltage, the behavior is the same, because the low-side is turned-on immediately. The following figure shows the device behavior during an over-voltage event. The output voltage rises with a slope of 100mV/µs, emulating in this way the breaking of the high-side MOSFET as an over-voltage cause. 14/24 L6731B LGate FB ...
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... L6731B Figure 8. OVP: the low-side MOSFET is turned-on in advance. The device realizes the over-current-protection (OCP) sensing the current both on the high- side MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in ● Peak Current Limit ● ...
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... Both MOSFETs are turned off and the soft-start capacitor is rapidly discharged with an internal switch. The device doesn't restart until the junction temperature goes down to 120°C and, in any case, until the voltage at the soft-start pin reaches 500mV. 16/24 L6731B VSS VCOMP I ...
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... L6731B. In fact voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6731B, neither for the over-current protection, given that during the off-time the valley-current-protection can operate in every case. The first advantage related to this feature is the possibility to realize extremely low conversion ratios ...
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... Vin L Vout Iout ESR ESR 2 Iout L 2 Cout ( Vin , min D max 2 Iout L Vout COUT 2 Cout Vout is the maximum duty cycle value that in the L6731D is 100%. For MAX 1 Vout I ( ESR L 8 Cout ) between 20% and 30% of the L (2) (3) (4) Vout ) (5) ) (6) Fsw L6731B ...
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... L6731B 6.3 Input capacitors The input capacitors have to sustain the RMS current flowing through them, that is: Where D is the duty cycle. The equation reaches its maximum value, I losses in worst case are: 6.4 Compensation network The loop is based on a voltage mode control internal/external reference voltage and scaled by the external resistor divider ...
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... Check the loop gain considering the error amplifier open loop gain. Figure 12. Asymptotic Bode plot of Converter's open loop gain 20/24 (R5, C18 and C19). The compensation network has to provide (13) ESR L Cout 1 (15 (17 order to obtain the desired converter bandwidth Vin Vosc (14) ESR Cout 1 (16 (18 (19 ESR L6731B IN ...
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... L6731B 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... L6731B inch TYP. MAX. 0.047 0.004 0.006 0.039 0.041 0.012 0.0089 0.197 0.201 0.252 0.260 0.173 0.177 0.0256 0° 8° 0.024 ...
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... L6731B 8 Revision history Table 7. Revision history Date Revision 22-Dec-2005 31-May-2006 26-Jun-2006 1 Initial release 2 New template, thermal data updated 3 Note page 5 deleted Revision history Changes 23/24 ...
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