ISL6556BCB Intersil, ISL6556BCB Datasheet

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ISL6556BCB

Manufacturer Part Number
ISL6556BCB
Description
IC CTRLR MULTIPHASE VRM10 28SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6556BCB

Applications
Controller, Intel VR10X
Voltage - Input
3 ~ 12 V
Number Of Outputs
4
Voltage - Output
0.84 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Optimized Multi-Phase PWM Controller
with 6-Bit DAC and Programmable Internal
Temperature Compensation for VR10.X
Application
The ISL6556B controls microprocessor core voltage
regulation by driving up to 4 synchronous-rectified buck
channels in parallel. Multi-phase buck converter architecture
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents.
The ISL6556B utilizes r
phase for adaptive voltage positioning (droop), channel-
current balancing, and overcurrent protection. To ensure the
accuracy of droop, a programmable internal temperature
compensation function is implemented to nullify the effect of
r
A unity gain, differential amplifier is provided for remote voltage
sensing. Any potential difference between remote and local
grounds can be eliminated using the remote-sense amplifier.
The precision threshold-sensitive enable input is available to
accurately coordinate the startup of the ISL6556B with Intersil
MOSFET driver IC. Dynamic-VID™ technology allows
seamless on-the-fly VID changes. The offset pin allows accurate
voltage offset settings that are independent of VID setting. The
ISL6556B uses 5V bias and has a built-in shunt regulator to
allow 12V bias using only a small external limiting resistor.
Ordering Information
PART NUMBER TEMP. (°C)
ISL6556BCB*
ISL6556BCBZ*
(Note)
ISL6556BCBZA
-T (Note)
ISL6556BCR*
ISL6556BCRZ*
(Note)
* Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DS(ON)
temperature sensitivity.
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
DS(ON)
28 Ld SOIC
28 Ld SOIC (Pb-free) M28.3
28 Ld SOIC Tape and
Reel (Pb-free)
32 Ld 5x5B QFN
32 Ld 5x5B QFN
(Pb-free)
®
1
current sensing in each
PACKAGE
Data Sheet
Dynamic VID™ is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved
PKG. DWG. #
M28.3
M28.3
L32.5x5B
L32.5x5B
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Precision Multi-Phase Core Voltage Regulation
• Precision r
• Internal Shunt Regulator for 5V or 12V Biasing
• Microprocessor Voltage Identification Input
• Threshold Enable Function for Precision Sequencing
• Overcurrent Protection
• Overvoltage Protection
• 2, 3, or 4 Phase Operation up to 1.5MHz per Phase
• QFN Package Option
• Pb-free Available (RoHS Compliant)
December 28, 2004
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Temperature and Life
- Adjustable Reference-Voltage Offset
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Low-Cost, Lossless Current Sensing
- Dynamic VID™ Technology
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
- No Additional External Components Needed
- OVP Pin to drive optional Crowbar Device
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
- QFN Near Chip Scale Package Footprint; Improves
Flat No Leads - Product Outline
PCB Efficiency, Thinner in Profile
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
DS(ON)
Current Sensing
ISL6556B
FN9097.4

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ISL6556BCB Summary of contents

Page 1

... ISL6556B uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. Ordering Information PART NUMBER TEMP. (°C) PACKAGE ISL6556BCB SOIC ISL6556BCBZ SOIC (Pb-free) M28.3 (Note) ISL6556BCBZA SOIC Tape and -T (Note) Reel (Pb-free) ISL6556BCR 5x5B QFN ISL6556BCRZ 5x5B QFN (Pb-free) (Note) * Add “ ...

Page 2

Pinouts 32 LEAD QFN TOP VIEW VID3 1 2 VID2 3 VID1 4 VID0 5 VID12.5 6 OFS 7 TCOMP REF ISL6556B PWM4 ...

Page 3

ISL6565BCB Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET REF VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB TCOMP T 3 ISL6556B OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START CLOCK ...

Page 4

ISL6565BCR Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET OFSOUT REF VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB TCOMP T 4 ISL6556B OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START ...

Page 5

... Typical Application of ISL6556BCB +5V FB COMP VCC TCOMP VDIFF VSEN RGND REF PGOOD OVP ISL6556BCB PWM1 VID4 ISEN1 VID3 PWM2 VID2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 EN GND R T VID_PGOOD (BUFFERED) 5 ISL6556B +12V VCC BOOT UGATE PVCC PHASE HIP6601B ...

Page 6

Typical Application of ISL6556BCR +5V COMP VCC FB OFSOUT VDIFF TCOMP VSEN RGND PGOOD REF OVP ISL6556BCR VID4 ISEN1 VID3 PWM1 VID2 PWM2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 GND ENLL +12V VID_PGOOD ...

Page 7

Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V ...

Page 8

Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), T Unless Otherwise Specified. (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS pin OSCILLATOR Accuracy Adjustment Range Sawtooth Amplitude Max Duty Cycle ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth ...

Page 9

... PWM1, PWM2, PWM3, PWM4 - Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. ...

Page 10

Operation Multi-Phase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multi-phase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost- effective and thermally ...

Page 11

Figures 14, 16 and 16 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the ...

Page 12

... ISL6556B The output of the error amplifier, V sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry that controls voltage regulation is illustrated in Figure 5. ...

Page 13

TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES VID4 VID3 VID2 VID1 VID0 ...

Page 14

... VID inputs during regulator operation. The power management solution is required to monitor the DAC inputs and respond to DYNAMIC VID D/A E 0.5V - ISL6556BCB GND VCC WITH ISL6556BCB (28-LEAD SOIC) DYNAMIC VID D/A E/A + 0.5V - ISL6556BCR GND VCC WITH ISL6556BCR (32-LEAD QFN) - 2.0V ...

Page 15

VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. The ISL6556B checks the VID inputs six times ...

Page 16

... ICs reach their POR level before the ISL6556B becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6556B with the HIP660X family of Intersil MOSFET drivers, which require 12V bias. 3. (ISL6556BCR only) The voltage on ENLL must be logic high to enable the controller. This pin is typically connected to the VID_PGOOD ...

Page 17

... VSEN falls below 0.6V with valid VCC or 1.5V otherwise. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. The PWM outputs remain low until VDIFF falls to the programmed DAC level when they enter a high-impedance state ...

Page 18

... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. ...

Page 19

Current Sensing The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and ISEN4. The resistors connected between these pins and the respective phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting ...

Page 20

ESR Case 2: 2π 2π -------------------------------------------- 0.75V ------------------------------------------------------------ - C ...

Page 21

Input Supply Voltage Selection The VCC input of the ISL6556B can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC ...

Page 22

... IN between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. ...

Page 23

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...

Page 24

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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