IC BUCK SYNC ADJ 6A 25MLP

FAN2106MPX

Manufacturer Part NumberFAN2106MPX
DescriptionIC BUCK SYNC ADJ 6A 25MLP
ManufacturerFairchild Semiconductor
SeriesTinyBuck™
TypeStep-Down (Buck)
FAN2106MPX datasheet
 

Specifications of FAN2106MPX

Internal Switch(s)YesSynchronous RectifierYes
Number Of Outputs1Voltage - Output3 ~ 21 V
Current - Output6AFrequency - Switching300kHz ~ 600kHz
Voltage - Input3 ~ 24 VOperating Temperature-10°C ~ 85°C
Mounting TypeSurface MountPackage / Case25-MLP
Power - Output2.8WMounting StyleSMD/SMT
Operating Temperature Range- 10 C to + 85 COutput Voltage0.4 V to 3.2 V
Primary Input Voltage24VNo. Of Outputs1
Output Current6ANo. Of Pins25
Filter TerminalsSMDOutput Current Max6A
Rohs CompliantYesInput Voltage Primary Max24V
For Use WithFEB167 - BOARD EVAL FOR FAN2106Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesFAN2106MPXTR  
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Circuit Description
PWM Generation
Refer to Figure 2 for the PWM control mechanism.
FAN2106 uses the summing-mode method of control to
generate the PWM pulses. An amplified current-sense
signal is summed with an internally generated ramp and
the combined signal is compared with the output of the
error amplifier to generate the pulsewidth to drive the
high-side MOSFET. Sensed current from the previous
cycle is used to modulate the output of the summing
block. The output of the summing block is also
compared against a voltage threshold set by the R
resistor to limit the inductor current on a cycle-by-cycle
basis. The R
resistor helps set the charging current
RAMP
for the internal ramp and provides input voltage feed-
forward function. The controller facilitates external
compensation for enhanced flexibility.
Initialization
Once V
exceeds the UVLO threshold and EN is
CC
HIGH, the IC checks for a shorted FB pin before
releasing the internal soft-start ramp (SS).
If the parallel combination of R1 and R
internal SS ramp is not released and the regulator does
not start.
Enable
FAN2106 has an internal pull-up to the ENABLE (EN)
pin so that the IC is enabled once V
UVLO threshold. Connecting a small capacitor across
EN and AGND delays the rate of voltage rise on the EN
pin. The EN pin also serves for the restart whenever a
fault occurs (refer to the Auto-Restart section). If the
regulator is enabled externally, the external EN signal
should go HIGH only after V
applications where such sequencing is required,
FAN2106 can be enabled (after the V
external control, as shown in Figure 21.
3.3n
Figure 21. Enabling with External Control
Soft-Start
Once internal SS ramp has charged to 0.8V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0V (T1.0), the fault latch is inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply V
before V
reaches its UVLO threshold. Normal
IN
CC
sequence for powering up would be VIN VCC EN.
© 2009 Fairchild Semiconductor Corporation
FAN2106 • Rev. 1.1.0
Soft-start time is a function of switching frequency.
LIM
is ≤ 1KΩ, the
BIAS
Cycling V
and resets the IC. In applications where external EN
signal is used, V
before the EN signal comes up to prevent skipping the
soft-start function.
exceeds the
Startup on Pre-Bias
CC
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until
internal SS ramp reaches 95% of V
helps the regulator start on a pre-biased output and
ensures that the pre-biased outputs are not discharged
is established. For
CC
during soft-start.
comes up) with
CC
Protections
The converter output is monitored and protected
FAN2106
against extreme overload, short-circuit, over-voltage,
under-voltage, and over-temperature conditions.
14
EN
Under-Voltage Shutdown
If the voltage on the FB pin remains below the under-
voltage threshold for 16 consecutive clock cycles, the
fault latch is set and the converter shuts down. This
protection is not active until the internal SS ramp
reaches 1.0V during soft-start.
Over-Voltage Protection
If voltage on the FB pin exceeds 115% of V
consecutive clock cycles, the fault latch is set and
shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
10
1.35V
EN
2400 CLKs
0.8V
FB
Fault
Latch
1.0V
Enable
0.8V
SS
3200 CLKs
T0.8
4000 CLKs
T1.0
Figure 22. Soft-Start Timing Diagram
or the EN pin discharges the internal SS
CC
and V
should be established
IN
CC
(~0.76V). This
REF
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