LT3582EUD-12#PBF Linear Technology, LT3582EUD-12#PBF Datasheet - Page 13

IC DC/DC CONV +/-12V 16-QFN

LT3582EUD-12#PBF

Manufacturer Part Number
LT3582EUD-12#PBF
Description
IC DC/DC CONV +/-12V 16-QFN
Manufacturer
Linear Technology
Type
Step-Up (Boost), Invertingr
Datasheet

Specifications of LT3582EUD-12#PBF

Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
2
Voltage - Output
±12V
Current - Output
350mA, 600mA
Voltage - Input
2.55 ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-WQFN Exposed Pad
Primary Input Voltage
3.6V
No. Of Outputs
2
Output Voltage
12V
Output Current
600mA
No. Of Pins
16
Operating Temperature Range
-40°C To +125°C
Msl
MSL 1 - Unlimited
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Frequency - Switching
-

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APPLICATIONS INFORMATION
CMDR: The Command Register is used to control various
functions of the chip. During shutdown and power-up the
CMDR is initialized to 00h.
The RSEL (Register Select) bits are functional only for
the LT3582. The LT3582-5 and LT3582-12 function as if
the RSEL bits are always “0”. These bits perform three
functions:
• Each RSEL bit instructs the chip whether to use the
• Each RSEL bit determines if I
• OTP programming only programs data to the bytes with
Setting the SWOFF bit immediately disables the Boost
and Inverting power switches and opens the output dis-
connect PMOS switch. It is recommended to set this bit
before writing new confi guration data. This can prevent
unexpected chip behavior while modifying the confi gura-
tion and also forces a soft-start after SWOFF is cleared
(see Soft-Start and Power-Up Sequencing ). Writing “1”
to the RST bit resets the internal I
register. Reading bit 6 of the CMDR returns the FAULT bit
indicating if an OTP programming attempt may have failed.
FAULT is cleared during reset, power-up, or by writing a “1”
to the CF (Clear Fault) bit. Conditions that set the FAULT
bit are (1) OTP programming in which the V
is too low or (2) attempted OTP programming when the
LOCK bit is set. OTP write attempts that set the FAULT bit
due to low V
the device should be discarded. Attempts to re-program
the OTP memory after the FAULT bit has been set are not
recommended. Finally, setting the WOTP bit starts the
OTP programming.
confi guration data from the corresponding OTP byte
(RSELx = 0) or the REG byte (RSELx = 1). Changing an
RSELx bit immediately updates the chip confi guration.
the corresponding OTP byte (RSELx = 0) or the REG
byte (RSELx = 1).
corresponding RSEL bits set high.
PP
voltage should be considered failures and
2
C reads return data from
2
C logic and the CMDR
PP
voltage
Table 1: LT3582 Series Register Map
OTP0/REG0 and OTP1/REG1: Data in addresses 00h and
01h is used to set the output voltages of the Boost and
Inverting converters respectively. See Setting the Output
Voltages for more information.
REGISTER
ADDRESS
LT3582/LT3582-5/LT3582-12
00h
01h
02h
04h
REGIS-
CMDR
NAME
REG0/
REG1/
REG2/
OTP0
OTP1
OTP2
TER
BIT
7:0
7:0
4:3
1:0 PUSEQ Power-Up Sequencing: 00 =
7
6
5
2
7
6
5
4
3
2
1
0
SWOFF Switches-Off
PDDIS Power-Down Discharge Enable.
RSEL2 Register Select 2 (0 = OTP2,
RSEL1 Register Select 1 (0 = OTP1,
RSEL0 Register Select 0 (0 = OTP0,
WOTP Write OTP Memory
NAME
V
FAULT
LOCK
IRMP
RST
BIT
PLUS
CF/
V
V
-
-
P
N
DESCRIPTION
V
BFh = 12.75V)
V
FFh = 13.95V)
Reserved, Write to 0
Lockout Bit: See the OTP
Programming Lockout Section.
V
V
RAMPP and RAMPN Pull-Up
Current: I
PUSEQ Must be 11 if Set.
Outputs Disabled, 01 = V
Ramp 1st, 10 = V
11 = Both Ramp Together
Clear Fault/OTP Programming
Fault
Reset
Reserved, Write to 0
1 = REG2)
1 = REG1)
1 = REG0)
OUTP
OUTN
OUTP
OUTP
Output Voltage (00h=3.2V,
Output Voltage (00h=1.2V,
Output Voltage Bit: Increase
by ~25mV
RAMP
= (2)
OUTP
IRMP
Ramp 1st,
OUTN
13
μA
3582512fb

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