SC4524ASETRT Semtech, SC4524ASETRT Datasheet - Page 13

• Manufacturer Part Number: SC4524ASETRT
• Description: IC STEP-DWN SW REG 2A 28V 8-SOIC
• Manufacturer: Semtech
• Type: Step-Down (Buck)r

Specifications of SC4524ASETRT

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Current - Output: 2A
• Frequency - Switching: 300kHz ~ 1.3MHz
• Voltage - Input: 3 ~ 28 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Power - Output: -
• Other names: SC4524ASETR

2
2
0
0
ω
ω
PWM
PWM
V
V
S
S
p
p
V
V
45
45
⋅
⋅


 
 








−
−
,
,
FB
FB
0
0
 ( )
 ( )
n
n
O
O
3
3
2
2
,
,
G
G
28
28
80
80
pF
pF
)
)
3
3


nF
nF
 (
 (


 
 


=
=
CA
CA


3
3


⋅
⋅
+
+
Applications Information (Cont.)
The block diagram in Figure 7 shows the control loops of a
buck converter with the SC4524A. The inner loop (current
loop) consists of a current sensing resistor (R
and a current amplifier (CA) with gain (G
loop (voltage loop) consists of an error amplifier (EA), a
PWM modulator, and a LC filter.
Since the current loop is internally closed, the remaining
task for the loop compensation is to design the voltage
compensator (C
For a converter with switching frequency F
inductance L
control (V
given by:
This transfer function has a finite DC gain
an ESR zero F
a dominant low-frequency pole F
and double poles at half the switching frequency.
⋅
⋅
22
22
22
22
⋅
⋅
R
R
⋅
⋅
+
+
0
0
6
6
/ s
/ s
22
22
S
S
 .
 .
R s
R s
.
.
 .
 .


FB
FB


k 3
k 3
⋅
⋅
3
3
ω
ω
 .
 .
2
2
⋅
⋅
ESR
ESR
⋅
⋅
R
R
R
R
ω
ω
n
n
R
R
⋅
⋅
C
C
C
C
0
0
C
C
C
C
G
G
G
G
R
R
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
A
ω
ω
V
V
V
V
V
V
V
V
0
0
π
π
REF
REF
22
22
Q
Q
⋅
⋅
7
7
7
7
7
7
o
o
o
o
c
c
c
c
PWM
PWM
PWM
PWM
7
7
Figure 7. Block diagram of control loops
C
C
C
C
C
C
C
C
5
5
5
5
8
8
8
8
Z
Z
5
5
5
5
8
8
8
8
F
F
p
p
0
0
C
C


+
+
C
C
−
−
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
≈
≈
=
=
=
=
3
3
=
=
C
O
O
+
+
3
3
-
-
⋅
⋅
C
C
CONTROLLER AND SCHOTTKY DIODE
CONTROLLER AND SCHOTTKY DIODE
) to output (V
s
s
)
)
0
0
3
3
0
0
. 0
. 0
 (
 (
0
0
R
R
. 0
. 0
 (
 (
R
R
−
−
−
−
−
−
−
−
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
=
=
≈
≈
≈
≈
O
O
⋅
⋅
2
2
g
g
EA
EA
g
g


R
R
⋅ π
⋅ π

ESR
ESR
C
C
⋅ π
⋅ π
2
2
=
=
Z
π
π
20
20
20
20
28
28
⋅ π
⋅ π
⋅ π
⋅ π
π
π
π
π
π
π
20
20
20
20
28
28
. 0
. 0
/
/
C5
C5
R7
R7
⋅
⋅
, output capacitance C
G
G
G
G
+
+
+
+
m
m
m
m
0
0
0
0
−
−


4
4
at
A
A
A
A
F
F
O
O
⋅ π
⋅ π
20
20
20
20
F
F
F
F
F
F
2
2
ω
ω
V
V
6
6
C
C
C
C
CA
CA
V
V
CA
CA






6
6
6
6
600
600
45
45


600
600
/ s
/ s
/ s
/ s
C
C
 Z
 Z
P
P
5
 Z
 Z
P
P
,
,
=
=
FB
FB
, R
⋅
⋅
⋅
⋅
O
O
2
2
n
n




COMP
COMP
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
R
R
R
R
⋅
⋅
5
5
O
O
5
5
80
80
log
log
log
log
log
log
log
log
0
0
0
0
pF
pF
20
20
20
20
⋅
⋅
⋅
⋅
R
R
)
)
R
R


R
R
R
R
R
R
3
3
nF
nF
G
G
G
G
Vramp
Vramp
9 .
9 .
9 .
9 .
R
R
R
R
ω
ω
ω
ω
Vc
Vc


 
 


7
⋅
⋅
⋅
⋅
,
,
6
6
0 .
0 .
3 .
3 .
, and C
0
0
7
7
7
7
7
7
7
7
0
0
PWM
PWM
PWM
PWM
S
S
p
p
S
S
⋅
⋅
⋅
⋅
p
p








 
 








−
−
⋅
⋅


 
 








−
−
0
0
0
0
 ( )
 ( )
0
0
 ( )
 ( )
3
3
3
3
,
,
,
,


G
G
28
28
G
G
28
28






C8
C8
CA
CA
3
3
3
3


MODULATOR
MODULATOR


V
V
0 .
0 .
 (
 (
=
=
=
=
=
=
 (
 (
CA
CA
CA
CA






3
3
O
O
3
3




⋅
⋅
⋅
⋅
3
3
O
+
+
+
+
PWM
PWM
5
5
V
V
⋅
⋅
⋅
⋅
22
22
22
22
22
22
22
22
R
R
) transfer function in Figure 7 is
R
R
⋅
⋅
⋅
⋅
+
+
+
+
⋅
⋅
ω
ω
6
6
6
6
/ s
/ s
8
/ s
/ s
22
22
22
22
S
S
).
22
22
S
S
−
−
 .
 .
 .
 .
R s
R s
R s
R s
Z
Z
9 .
9 .
Rs
Rs
.
.
 .
 .




.
.
 .
 .
k 3
k 3
k 3
k 3


⋅
⋅
⋅
⋅
ω
ω
ω
ω
=
=
 .
 .
 .
 .
2
2
⋅
⋅
dB
dB
2
2
⋅
⋅
ESR
ESR
⋅
⋅
ESR
ESR






⋅
⋅
⋅
⋅
n
n
n
n
0
0
0
0
0
0
ω
ω
ω
ω
R
R
0
0
π
π
π
π
0
0
Io
Io
Q
Q
Q
Q
⋅
⋅
⋅
⋅
F
F
p
p
p
p
F
F
0
0
0
0
ESR
ESR
C
C
C
C
P




+
+
+
+
C
C
C
C
−
−
−
−
−
−


≈
≈
≈
≈
3
3
3
3
at
O
O
O
O
3
3
3
3
C
C
C
C
6
6
s
s
C
C
SW
SW
s
s
)
)
3
3
3
3
)
)
R
R
R
R
=
=
=
=
O
O
O
O
O
⋅
⋅
⋅
⋅
2
2
⋅
⋅
2
2
O
O




C
C
C
C
2
2
=
=
2
2


=
=
3
3
. 0
. 0
. 0
. 0
and loading R, the
/
/
/
/
⋅
⋅
⋅
⋅
,
,
O
O
⋅ π
⋅ π
O
O
⋅ π
⋅ π
0 .
0 .
3 .
3 .
2
2
2
2
ω
ω
ω
ω
V
V
V
V
V
V
CA
V
V
45
45
45
45
,
,
,
,
FB
FB
FB
FB
O
O
2
2
2
2
n
n
n
n
O
O
L1
L1
=28). The outer






80
80
80
80
Fig.8
Fig.8
pF
pF
pF
pF
)
)
)
)
nF
nF
nF
nF
Co
Co
Resr
Resr
=
=




 
 
 
 




5
5
⋅
⋅
⋅
⋅
0
0
0
0
SW
(8)
s
9 .
9 .
=6.mW)
, output




3
3
3
3
dB
dB
⋅
⋅
⋅
⋅
ω
ω
ω
ω
Vo
Vo
22
22
22
22
R4
R4
R6
R6
Z
Z
Z
Z
=
=
=
=
⋅
⋅
⋅
⋅
0
0
0
0
R
R
R
R
ESR
ESR
ESR
ESR
−
−




−
−
6
6
6
6
C
C
C
C
Including the voltage divider (R
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F
at F
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
Therefore, the procedure of the voltage loop design for
the SC4524A can be summarized as:
() Plot the converter gain, i.e. control to feedback transfer
function.
(2) Select the open loop crossover frequency, F
0% and 20% of the switching frequency. At F
required compensator gain, A
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at F
⋅
⋅
⋅
⋅
O
O
O
O




3
3
3
3
,
,
,
,
0 .
0 .
0 .
0 .
3 .
3 .
3 .
3 .
-60
-60
P
-30
-30
60
60
30
30
0
0
. The integrator is used to boost the gain at low












1K
1K
A
A
A
A
=
=
=
=
Figure 8. Bode plots for voltage loop design
C
C
C
C
5
5
5
5
=
=
=
=
9 .
9 .
−
−
−
−
9 .
9 .
20
20
20
20
dB
dB
dB
dB
Fp
Fp
⋅
⋅
⋅
⋅
log
log
log
log
10K
10K


 
 








G
G
28
28
Fz1
Fz1
CA
CA


FREQUENCY (Hz)
FREQUENCY (Hz)
⋅
⋅
R
R
6
6
S
S
Z
 .
 .


, and a high frequency pole
⋅
⋅
C
. In typical applications with
2
2
⋅
⋅
Fc
Fc
100K
100K
0
0
π
π
4
F
F


C
C
−
−
and R
3
3
C
C
C
Fp1
Fp1
Fz
Fz
can be estimated by
O
O
⋅
⋅
2
2
⋅
⋅
⋅ π
⋅ π
V
V
6
Fsw/2
Fsw/2
V
V
), the control to
FB
FB
SC4524A
O
O
1M
1M
80
80


 
 


⋅
⋅
C
0
0
, between
C
, find the
(9)


3
3
⋅
⋅
22
22
10M
10M
3
⋅
⋅
0
0
−
−
6
6
⋅
⋅


. 3
. 3
0 .
0 .