L6726ATR STMicroelectronics, L6726ATR Datasheet - Page 15

IC CTRLR PWM SGL PHASE 8-SOIC

L6726ATR

Manufacturer Part Number
L6726ATR
Description
IC CTRLR PWM SGL PHASE 8-SOIC
Manufacturer
STMicroelectronics
Type
Step-Down (Buck)r
Datasheet

Specifications of L6726ATR

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
Adj to 0.8V
Frequency - Switching
270kHz
Voltage - Input
1.5 ~ 12 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Output Current
1.5 A
Input Voltage
4.1 V to 13.2 V
Operating Temperature Range
- 40 C to + 150 C
Mounting Style
SMD/SMT
For Use With
497-9046 - BOARD EVAL BASED ON L6726A497-6364 - BOARD DEMO FOR TS4995EIJT497-6259 - BOARD EVAL 1PH STPDN CONV L6726A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Power - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-5906-2

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L6726A
8
8.1
8.2
Application details
Output voltage selection
L6726A is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to
be within ±1% tolerance over line and temperature variations between 0 °C and 70 °C
(excluding output resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be achieved by adding a resistor R
and ground. Referring to
where V
Compensation network
The control loop shown in
transconductance type with fixed gain (3.3 ms typ.). The FB voltage is regulated to the
internal reference, thus the output voltage is fixed accordingly to the output resistor divider
(when present).
Transconductance error amplifier output current generates a voltage across Z
compared to oscillator saw-tooth waveform to provide PWM signal to the driver section.
PWM signal is then transferred to the switching node with V
filtered by the output filter.
Figure 8.
The converter transfer function is the small signal transfer function between the voltage at
the output node of the EA (COMP) and V
conjugate) at frequency F
REF
is 0.8 V.
PWM control loop
ΔV
OSC
OSC
Figure
LC
Figure 8
C
R
depending on the L-C
F
COMPARATOR
F
V
Doc ID 12754 Rev 4
COMP
1, the steady state DC output voltage will be:
OUT
_
+
PWM
is a voltage mode control loop. The error amplifier is a
Z
C
F
=
P
OTA
V
OUT
REF
. This function has a double pole (complex
+
_
V
OUT
1
V
IN
R
REF
FB
+
OS
resonance and a zero at F
---------- -
R
R
L
OS
FB
R
FB
IN
amplitude. This waveform is
OUTPUT
DIVIDER
R
C
ESR
OUT
Application details
OS
V
OUT
between FB pin
F
, which is
ESR
15/35

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