L6730TR STMicroelectronics, L6730TR Datasheet
L6730TR
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L6730TR Summary of contents
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... Low voltage distributed DC-DC ■ niPOL converters ■ DDR memory supply ■ DDR memory bus termination supply DS(on) Table 1. Device summary Order codes L6730 L6730TR L6730B L6730BTR Doc ID 11938 Rev 3 L6730 L6730B HTSSOP20 Package Packing HTSSOP20 Tube HTSSOP20 Tape and reel ...
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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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L6730 - L6730B 6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary description 1 Summary description The controller is an integrated circuit designed using BiCMOS-DMOS, v5 (BCD5) technology that provides complete control logic and protection for high performance, step- down DC/DC and niPOL converters designed to drive N-Channel MOSFETs ...
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L6730 - L6730B 1.1 Functional description Figure 1. Block diagram PGOOD OCL Monitor SS/INH Protection and Ref SYNCH OSC EAREF PGOOD + SINK/OVP/UVLO* - MASKING TIME TMASK ADJUSTMENT Note: In the L6730B the multifunction pin is: CC/OVP/UVLO. V =4.5V to14V ...
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Summary description 1.2 Application circuit Figure 2. Application circuit SYNCH V CCDR R R H_OSC H_SOU R R L_OSC L_SOU SHORT PIN NOTE 1: In module application it is recommended to place the short pin on the module where device ...
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L6730 - L6730B 2 Electrical data 2.1 Maximum rating Table 2. Absolute maximum ratings Symbol BOOT - PHASE V V HGATE - PHASE V BOOT V PHASE OCH Pin PGOOD Pin OTHER PINS 2.2 Thermal data ...
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Pin connections and functions 3 Pin connections and functions Figure 3. Pins connection (top view) Note: In the L6730B the multifunction pin is: CC/OVP/UVLO. Table 4. Pin connection Pin n. Name 1 PGOOD DELAY 2 SYNCH SINK/OVP/UVLO L6730 3 CC/OVP/UVLO ...
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L6730 - L6730B Table 4. Pin connection (continued) Pin n. Name T 4 MASK 5 GND COMP 8 SS/INH 9 EAREF 10 OSC Description The user can select two different values for the leading edge blanking time ...
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Pin connections and functions Table 4. Pin connection (continued) Pin n. Name 11 OCL 12 OCH 13 PHASE 14 HGATE 15 BOOT 16 PGND 17 LGATE V 18 CCDR PGOOD - Thermal PAD 10/52 Description A ...
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L6730 - L6730B 4 Electrical characteristics 25°C unless otherwise specified CC A Table 5. Electrical characteristics Symbol Parameter V supply current CC V stand by current quiescent current CC Power-ON ...
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Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter I I.I. bias current FB Ext Ref Clamp V Error amplifier offset OFFSET G Open loop voltage gain V GBWP Gain-bandwidth product SR Slew-rate Gate drivers R High side source resistance ...
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L6730 - L6730B Table 6. Thermal characterizations (V Symbol Oscillator f Initial accuracy OSC Output voltage (1.2V MODE) V Output voltage FB Output voltage (0.6V MODE) V Output voltage Parameter Test condition OSC = OPEN; ...
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Device description 5 Device description 5.1 Oscillator The switching frequency is internally fixed to 400 kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging an internal capacitor (F kHz). This current can be varied using ...
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L6730 - L6730B 5.2 Internal LDO An internal LDO supplies the internal circuitry of the device. The input of this stage is the V pin and the output ( the V CC Figure 5. LDO block diagram 4.5V÷14V ...
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Device description Figure 6. Bypassing the LDO 5.4 Internal and external references It is possible to set two internal references, 0.6 V and 1 provide an external reference from 2.5 V. The maximum value of ...
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L6730 - L6730B 5.5 Error amplifier Figure 7. Error amplifier reference V CCDR 5.6 Soft-start When both V and V CC pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp ...
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Device description The output of the error amplifier is clamped with this voltage (Vss) until it reaches the programmed value. No switching activity is observable if V MOSFETs are off. When Vss is between 0.5 V and 1.1 V the ...
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L6730 - L6730B protection on page V reaches 3.5 V. After that the over current-protection triggers the HICCUP mode SS (L6730). With the L6730B there is the possibility to set the HICCUP mode or the constant current mode after the ...
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Device description Figure 12. Sink mode disabled: Inductor current during and after soft-start (L6730) 5.7 Driver section The high-side and low-side drivers allow for the use of different types of power MOSFETs (also multiple MOSFETs to reduce the R low-side ...
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L6730 - L6730B negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. Figure 13. Dead times 5.8 Monitoring and protection The output voltage is monitored by the ...
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Device description turned on until V CC forced high (4.5 V typ over voltage is detected. Figure 14. PGOOD signal Figure 15. OVP not latched 22/52 is toggled (see Figure 16). In case of latched-mode OVP the OSC ...
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L6730 - L6730B Figure 16. OVP latched There is an electrical network between the output terminal and the FB pin and therefore the voltage at this pin is not a perfect replica of the output voltage. If the converter can ...
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Device description Figure 17. OVP with sink enabled: the low-side MOSFET is turned-on in advance Figure 18. OVP with sink disabled: delay on the OVP operation The L6730B can always sink current and so the OVP will operate always in ...
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L6730 - L6730B enters in HICCUP mode (L6730): the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10 µA and when the voltage at the SS pin reaches 0.5 V the ...
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Device description Figure 20. Peak overcurrent-protection in constant-current-protection (L6730B) V OUT Figure 21. Peak OCP in case of heavy overcurrent (L6730B) V OUT OUT If the current is higher than the valley OCP threshold ...
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L6730 - L6730B Working with BUS, setting the UVLO at 8.6 V can be very helpful to limit the input current in case of BUS fall. Figure 22. Valley OCP (L6730B) V OUT I L 5.9 Adjustable ...
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Device description Table 7 shows how to set the different options through an external resistor divider: Figure 23. External resistor Table 7. S/O/U and CC/O/U pin R1 N.C 11KΩ 6.2KΩ 4.3KΩ 2.7KΩ 1.8KΩ 1.2KΩ 0Ω 5.11 Synchronization The presence of ...
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L6730 - L6730B The phase shift between master and slaves is approximately done 180°. Figure 24. Synchronization 5.12 Thermal shutdown When the junction temperature reaches 150°C ±10°C, the device enters in thermal shutdown. Both MOSFETs are turned OFF and the ...
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Device description Figure 25 -> 0.5 V@820 kHz 5.14 Bootstrap anti-discharging system This built-in anti-discharging system keeps the voltage going across the bootstrap capacitor from going below 3 internal comparator senses the voltage across ...
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L6730 - L6730B 5.14.1 Fan power supply failure In many applications the fan is driven motor that uses a DC/DC converter. Often only the speed of the motor is controlled by varying the voltage applied to the ...
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Device description effectively turned-on and the regulation can be lost. Thanks to the “bootstrap anti- discharging system” the bootstrap cap is always kept charged. The following picture shows the behaviour of the device in the following conditions -> ...
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L6730 - L6730B 6 Application details 6.1 Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current ...
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Application details 6.2 Output capacitors The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. ...
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L6730 - L6730B 6.4 Compensation network The loop is based on a voltage mode control the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output V pulse-width modulated (PWM) with an amplitude ...
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Application details 0 dB axis with -20 dB/decade slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation networks, the following suggestions may be used: ● Modulator singularity frequencies: ● Compensation network singularity frequencies: ...
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L6730 - L6730B 6.5 Two quadrant or one quadrant operation mode (L6730) After the soft-start phase the L6730 can work in source only (one quadrant operation mode sink/source (two quadrant operation mode), depending on the setting of the ...
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L6730 demonstration board 7 L6730 demonstration board 7.1 Description L6730 demonstration board realizes in a four layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from ...
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L6730 - L6730B 7.2 PCB layout Figure 33. Top layer Figure 35. Signal ground layer Figure 34. Power ground layer Figure 36. Bottom layer Doc ID 11938 Rev 3 L6730 demonstration board 39/52 ...
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L6730 demonstration board Figure 37. Demonstration board schematic Table 8. Demonstration board part list Reference Value R1 820Ω N.C. R4 10Ω 1% 100mW R5 11K 1% 100mW R6 6K2 1% 100mW R7 4K3 1% 100mW R8 2K7 1% ...
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L6730 - L6730B Table 8. Demonstration board part list (continued) Reference Value R14 1K 1% 100mW R15 1K 1% 100mW R16 4K7 1% 100mW R17 N.C. R18 2.2Ω R19 2.2Ω R20 10K 1% 100mW R21 N.C. R22 N.C. R23 C1 ...
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L6730 demonstration board Table 9. Other inductor manufacturer Manufacturer WURTH ELEKTRONIC SUMIDA EPCOS TDK TOKO COILTRONICS Table 10. Other capacitor manufacturer Manufacturer TDK NIPPON CHEMI-CON PANASONIC 42/52 Series Inductor value (µH) 744318180 CDEP134-2R7MC-H HPI_13 T640 SPM12550T-1R0M220 FDA1254 HCF1305-1R0 HC5-1R0 Series ...
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L6730 - L6730B 8 I/O Description Figure 38. Demonstration board Table 11. I/O functions Symbol Input (Vin-Gin) Output (V -G OUT OUT V -GND CCDR TP1 The input voltage can range from 1.8V to 14V. If the ...
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I/O Description Table 11. I/O functions (continued) Symbol TP2 TP3 SYNCH PWRGD DIP SWITCH Table 12. Dip switch UVLO 12V 12V 12V 12V 44/52 This test point is connected to the Tmask pin (see This test ...
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L6730 - L6730B 9 Efficiency The following figures show the demo board efficiency versus load current for different values of input voltage and switching frequency: Figure 39. Demonstration board efficiency 400 kHz 95.00% 90.00% 85.00% 80.00% 75.00% Figure 40. Demonstration ...
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Efficiency Figure 41. Demonstration board efficiency 1 MHz 95.00% 90.00% 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% Figure 42. Efficiency with 2xSTS12NH3LL+2XSTSJ100NH3LL 0.96 0.95 0.94 0.93 0.92 0.91 0.9 0.89 0.88 0.87 3 46/52 Fsw=1MHz Iout (A) ...
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L6730 - L6730B 10 POL demonstration board 10.1 Description A compact demonstration board has been designed to manage currents in the range of 10 Figure 39 shows the schematic and capacitors (MLCCs) have been used on the input ...
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POL demonstration board Table 13. Pol demonstration board part list (continued) Reference Value R11 15Ω 1% 100mW R12 4K7 1% 100mW R13 1K 1% 100mW R14 2.2Ω R15 2.2Ω C1-C7 220nF C6- C19-C20-C9 100nF C2 C11 N.C. C12 68nF C13 ...
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L6730 - L6730B 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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Package mechanical data Figure 45. Package dimensions 50/52 Doc ID 11938 Rev 3 L6730 - L6730B ...
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L6730 - L6730B 12 Revision history Table 15. Document revision history Date 21-Dec-2005 29-May-2006 07-Dec-2009 Revision 1 Initial release 2 New template, thermal data updated 3 Updated Table 4 on page 8 Doc ID 11938 Rev 3 Revision history Changes ...
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