L6722TR STMicroelectronics, L6722TR Datasheet

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Features ■ 2A integrated gate drivers ■ 0.8V reference ■ 1% output voltage accuracy ■ Adjustable reference offset ■ Precise current sharing and OCP across LS MOSFETS ■ Constant over current protection ■ Feedback disconnection ■ LSLESS allows managing pre-bias ...

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Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Application circuit . . . . . . ...

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L6722 9.6 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Typical application circuit and block diagram 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical application circuit GND VCC IN 4 PGND 1, 26 SGND R 18 OSC OSC/INH/FLT 19 REF_IN 20 ...

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L6722 Figure 2. Typical application circuit - droop enabled GND VCC IN 4 PGND 1, 26 SGND R 18 OSC OSC/INH/FLT 19 REF_IN 20 REF_OUT 36 COMP VSEN ...

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Typical application circuit and block diagram 1.2 Block diagram Figure 3. Block diagram VCC VCC PGND HS1 PGND SGND SGND OSC / INH / FLT DIGITAL SOFT START 6/34 VCC PGND VCC LS1 HS2 LS2 LOGIC PWM LOGIC PWM ...

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L6722 2 Pins description and connection diagrams Figure 4. Pins connection (top view) VSEN COMP SGND VCC N.C. LGATE1 PGND LGATE2 2.1 Pin description Table 1. Pins description Pin# Name 1 VSEN COMP 4 SGND 5 VCC ...

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Pins description and connection diagrams Table 1. Pins description (continued) Pin# Name 9 LGATE2 10 LGATE3 11 BOOT1 12 UGATE1 13 PHASE1 14 BOOT2 15 UGATE2 16 PHASE2 17 BOOT3 18 UGATE3 19 PHASE3 20 N.C. 21 PGOOD 22 ...

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L6722 Table 1. Pins description (continued) Pin# Name OSC / INH / 23 FLT 24 N.C. 25 REF_IN 26 REF_OUT 27, 28 N.C. 29 SGND 30 FBR 31 FBG ISEN3 ISEN1 35 CS+ 36 CS- THERMAL ...

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Pins description and connection diagrams 2.2 Thermal data Table 2. Thermal data Symbol Thermal Resistance Junction to Ambient R thJA (Device soldered on 2s2p PC Board) T Maximum Junction Temperature MAX T Storage Temperature Range STG T Junction Temperature ...

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L6722 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V to PGND Boot Voltage BOOTx PHASEx UGATEx PHASEx LGATEx, PHASEx, to PGNDx All other Pins to PGNDx Positive ...

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Electrical specifications Table 4. Electrical characteristics (continued 12V±15 Symbol Parameter Reference k Output Voltage Accuracy REF Error amplifier and remote buffer Gain 0 SR Slew Rate RB DC Gain Remote Buffer Common ...

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L6722 4 Device description L6722 is multi-phase PWM controller with embedded high current drivers that provides complete control logic and protections for a high performance step-down DC-DC voltage regulator. Multi-phase buck is the simplest and most cost-effective topology employable to ...

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Driver section 5 Driver section The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent RdsON), maintaining fast switching transition. The drivers for the high-side mosfets use BOOTx pins for supply ...

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L6722 ● Drivers' power is the power needed by the driver to continuously switch on and off the external mosfets function of the switching frequency and total gate charge of the selected mosfets. It can be quantified ...

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Current sharing loop and current reading 6 Current sharing loop and current reading L6722 embeds two separate Current-Reading circuitries used to perform Current-Sharing and OCP through ISENx pins and Voltage-Positioning through CS+ and CS- pins (See Current-sharing control-loop and ...

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L6722 7 Output voltage positioning Output voltage positioning is performed by programming the external resistor divider and by correctly designing Droop Function and Offset to the reference (Optional). The output voltage is then driven by the following relationship (See Both ...

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Output voltage positioning Figure 8. Offset definition (margin mode) Ref REF_OUT M1 M2 ● No Offset (M1=1; M2=0) ● Positive Margin (M1=0; M2=0) ● Negative Margin (M1=0; M2=1) Offset resistors may be simply defined as follow V TARGET POS ...

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L6722 Time constant matching between the inductor (L / DCR) and the current reading filter ⋅ required to implement a real equivalent output impedance of the system avoiding over and/or under shoot ...

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Output voltage positioning 7.3 Maximum duty cycle limitation To provide proper time for current-reading in order to equalize the current carried by each phase, the device implements a duty-cycle limitation. This limitation is not fixed but it is linearly ...

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L6722 8 Soft start L6722 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. The device increases the reference from zero up to the programmed value in 2048 ...

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Output voltage monitor and protections 9 Output voltage monitor and protections L6722 monitors through pin VSEN the regulated voltage and compares this voltage with the one present at the REF_IN pin to manage the OVP, UVP and PGOOD conditions. ...

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L6722 Figure 12. output voltage protections and typical principle connections (INH = Preliminary OVP FBR Monitor UVLO VCC UVLO OVP 9.4 Feedback disconnection Output voltage i monitored by the device in two different points: ● Remotely, through ...

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Output voltage monitor and protections 9.5 PGOOD open-drain signal set free after the soft-start sequence has finished pulled low when the output voltage drops below -150mV of the programmed voltage. 9.6 Over-current protection The ...

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L6722 V ------------------------------------------ - = I + PEAK OCPx Where V is the UVP threshold, (inductor saturation must be considered). When that outMIN threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device ...

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Oscillator 10 Oscillator The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel internally fixed at 100kHz so that the ...

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L6722 11 System control loop compensation The control loop is composed by the Current Sharing control loop (See Voltage control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in ...

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System control loop compensation ⋅ ● ------------------ - PWM = ∆V 5 OSC amplitude and has a typical value of 4V. Removing the dependence from the Error Amplifier gain, so assuming this gain high ...

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L6722 to move ω ● Increase C F phase margin. Having the fastest compensation network gives not the confidence to satisfy the requirements of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, ...

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Layout guidelines 12 Layout guidelines Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in ...

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L6722 Remote Sense Connection must be routed as parallel nets from the FBG/FBR pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a ...

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Layout guidelines Figure 19. VFQFPN36 Mechanical data & package dimensions mm DIM. MIN. TYP. MAX. A 0.800 0.900 1.000 A1 0.020 0.050 A2 0.650 1.000 A3 0.250 b 0.180 0.230 0.300 D 5.875 6.000 6.125 D2 1.750 3.700 4.250 ...

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L6722 13 Revision history Table 5. Revision history Date Revision 14-Apr-2006 1 Initial release. 13 Revision history Changes 33/34 ...

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... Revision history Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...