L6722TR STMicroelectronics, L6722TR Datasheet - Page 17

IC BUCK ADJ 2A TRPL 36VFQFPN

L6722TR

Manufacturer Part Number
L6722TR
Description
IC BUCK ADJ 2A TRPL 36VFQFPN
Manufacturer
STMicroelectronics
Type
Step-Down (Buck)r
Datasheet

Specifications of L6722TR

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
3
Voltage - Output
Adj to 0.8V
Current - Output
2A
Frequency - Switching
100kHz
Voltage - Input
12V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
36-VFQFN, 36-VFQFPN
Power - Output
3.5W
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5904-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
L6722TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
L6722TR
Manufacturer:
ST
0
L6722
7
7.1
Output voltage positioning
Output voltage positioning is performed by programming the external resistor divider and by
correctly designing Droop Function and Offset to the reference (Optional). The output voltage is
then driven by the following relationship (See
Both DROOP and OFFSET function can be disabled: see
details.
L6722 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any
additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating for board and connector losses. The device
senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated
voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and
guarded by a power plane results in common mode coupling for any picked-up noise.
When regulating output voltages higher than the reference, it is possible to insert a resistor
divider between FBR, FBG and the regulated voltage as reported in
important for the external divider to have a value negligible with respect to the remote buffer
impedance that has 64k resistors.
Figure 7.
Offset and margining-mode (optional)
Positive / negative offset can be added to the programmed reference by connecting proper
network resistor between the REF_OUT and REF_IN pins. In this way is possible to manage
margining-mode by adding small offsets (positive or negative) to the regulated voltage, in order
to test the loading-circuitry in different operative conditions to check for the reliability of the
system designed.
Referring to
as the device is enabled. By correctly designing R
may be added to the reference voltage according to the status of the control signals M1 and
M2. Different operating conditions can be then considered:
Ref
REF_OUT
Voltage positioning
Figure
8, a constant current (I
R
C
OS
OS
REF_IN
V
FB
OUT
=
OS
R
(
R
FB
Ref
F
=12µA) is sourced from the REF_IN pin as soon
Figure
)
OS1
COMP
C
F
R1
--------------------- -
7):
and R
R2
+
R2
VSEN
Section 7.1
OS2
, positive and negative offset
Figure
64k
7 Output voltage positioning
and
64k
R
1
(Remote Sense)
Section 7.2
FBR
7. In this case it is
To Vout
R
2
FBG
for
17/34

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